Military Embedded Systems - Fall 2005 - Volume 1 Number 2

Application
Performance enchancements
2.5 watt power requirement and the need
for a larger mechanical footprint and
(relative) lack of scalability.
The use of RAM, either DRAM or
SRAM, as a buffer introduces the new
design challenge of what happens to
the integrity of the drive in the event of
a power disturbance. RAM is a volatile
memory architecture and if power is lost
during a write operation, not only is the
data lost, there is a good possibility that
error correction and checksum of a particular
sector won’t match the data of that
Host
System
Data Sweep on 2 GB Solid-State
Storage Device
R/B
PWR OUT
V IN
Time/s
Figure 1
sector. The next time
the controller goes to
access that location, it
sees the discrepancy,
considers the sector
bad, and may use one
of a finite number of
spares. If this happens
too often, the drive
can cease to operate
because there are no
spares remaining.
Solid-state drive
designers attempt to
overcome this scenario
by integrating some
type of optional power
holdup circuit. This
usually involves either
a battery backup or
large capacitor circuit,
which can significantly
increase the mechanical
dimensions of the
drive. The circuit is
designed to allow the
contents of the RAM
buffer to be properly written to the nonvolatile
storage components and perform
an orderly shutdown. It is important to note
that this does not guarantee that the file
being written won’t be truncated. It may
not be a useful file, but at least the drive is
not corrupted.
An alternative solution is to design the
solid state drive to utilize the smallest
buffer possible. Only the highest end of
data recording applications truly requires
data rates in excess of about 15 MBps,
so other more transactional types of
SOLID-STATE DRIVE CONTROLLER
VOLTAGE DETECTION
AND REGULATION
READY/BUSY
PWR
ADDRESS/DATA/CONTROL
LOGIC
SOLID-STATE DRIVE
(ANY FORM FACTOR)
512-BYTE BUFFER
SOLID-STATE MEMORY ARRAY
applications may be willing to sacrifice
some speed for a high level of drive integrity.
Additional reliability can be achieved
by also integrating some voltage detection
circuitry to allow the storage solution to
make some very rapid decisions and perform
an orderly shutdown.
The optimal solution is to integrate as
much of this technology into the controller
architecture itself so that mechanical footprints
can be minimized. Figure 2 diagrams
how a controller with voltage detection,
regulation, and logic circuitry can be combined
with a solid-state memory array to
collectively maximize drive integrity.
More solid state drives for
military
The application-enhancing ruggedness,
scalability, advanced data security, and
power management capabilities realized
by incorporating solid state technology
into military applications are still being
discovered as designers replace existing
mechanical and magnetic drives and
add features to new designs. These new
features cannot, however, come at the
expense of increased size and power
consumption – especially in wearable or
battery-operated field computers.
Therefore, storage technologies tailored
to the military market must continue to
evolve.
Gary Drossel is
r e s p o n s i b l e f o r
managing marketing and
business development
for SiliconSystems’
complete product line.
A 15-year industry veteran, he has played
a leading role in developing the company’s
marketing strategy, including product
roll-out and customer introduction.
Drossel received a BS in electrical and
computer engineering from the University
of Wisconsin.
To learn more, contact Gary at:
SiliconSystems, Inc.
26940 Aliso Viejo Parkway
Aliso Viejo, CA 92656
Tel: 949-900-9400
Fax: 949-900-9500
E-mail: gdrossel@siliconsystems.com
Website: www.siliconsystems.com
Figure 2
48 / October 2005 Military EMBEDDED SYSTEMS