Embedded Computing Design - OpenSystems Media

input, feedback, and communication from
all parties involved.
The ISO’s website states that standards are
developed when “the need for a standard
is felt by an industry or business sector,
which communicates the requirement to
one of ISO’s national members. In order
to use resources most efficiently, ISO
only launches the development of new
standards for which there is clearly a
market requirement.”
The desire for RapidIO’s ISO recognition
was driven by key original equipment
manufacturers (OEMs) and by the RapidIO
Trade Association, which engaged with
the ECMA, originally called the European
Computer Manufacturers Association,
out of Geneva, Switzerland. Through the
ECMA, a liaison working group, TC42,
was formed to help facilitate the adoption
of the standard.
The other significant development for
RapidIO was the first peer-to-peer RapidIO
exchange that recently took place on two
of Thales Computers’ PowerNode3 cards
equipped with two RapidIO PMCs (see
Figure 1).
RapidIO’s 3-layer hierarchical architecture includes the physical layer at the low end,
which mediates device-level interfaces and electrical characteristics; the transport layer that
enables the correct routing of packets from sender to recipient; and the layer that defines
packet formats and the overall protocol, the logical layer.
RapidIO has been designed to minimize transaction overhead, which in turn reduces
latency and maximizes bandwidth. The switched nature of RapidIO enables it to provide
both multicast routing (sending a packet to multiple connected devices), and source
routing (sending a packet only to a specific source-defined destination device). Source
routing means that the transaction is routed according to the destination ID specified by
the source device.
Benefits for embedded applications
Because of its relatively small packet size (maximum data payload of 256 bytes), as well
as its ability to forward messages prior to complete receipt, a key feature of RapidIO is
that it maximizes throughput and minimizes latency during message routing.
With these basic attributes in mind, it is useful to consider how RapidIO can play a role
in both existing legacy systems and new systems. Legacy systems especially benefit from
the transparency of RapidIO, since these systems typically utilize one or more generations
of memory-mapped I/O software. RapidIO’s load/store architecture, which is similar to
PCI, enables system designers to map a full PCI bus, including interrupts, while using the
existing software drivers.
RapidIO’s physical characteristics, such as low power consumption and a limited silicon
footprint (transistor count), are ideal for harsh environments. Again, both new and legacy
systems benefit, since low power draw and space efficiency are primary concerns. The low
pin count of RapidIO also enables designers to preserve user-defined pins for existing or
new applications.
Figure 1
Phase II of Thales’ expansion of RapidIO
on its processor cards is to build a wider topology
of four cards, and ultimately expand
the exchange on up to 12. Additionally,
the company’s Serial RapidIO cards are
due out towards the end of Q3 2004.
With these recent developments, the embedded
industry will see the expansion of
RapidIO in even more products to increase
efficiency and meet today’s embedded
system requirements.
A RapidIO overview
Particularly suited for systems that incorporate
multiple devices in a tightly
coupled architecture, such as real-time
embedded applications, RapidIO provides
all of the necessary tools to facilitate data
movement in the control plane.
RSC #27 @ www.embedded-computing.com/rsc
Embedded Computing Design Summer 2004 / 27