Embedded Computing Design - OpenSystems Media

arithmetic, implementing algorithms in
FPGAs or ASICs gives the designer the
ability to independently control the number
of bits used to represent each number
in the algorithm. Using too may bits can
be costly – a 40% increase in the number
of bits in a multiplier can double its area
in silicon – but using too few can lead to
overflows or instabilities. When choosing
tools for implementing DSP algorithms
in silicon, designers should evaluate tools
that help automate this floating-point to
fixed-point conversion process.
6
Rule #6
Keep your options open
with vendor-independent,
technology-independent flow.
As designers, we are all increasingly
under pressure to cut costs, which often
leads to having to select the supplier who
can provide the lowest price, the best
availability, etc. The tools available in the
market fall into two categories.
Vendor-supplied tools are available from
companies offering FPGA devices for
DSP and provide integrated environments
spanning graphical design entry, IP
block libraries, and RTL simulation and
synthesis tools. But, these tools offer
libraries of DSP functions that can only
target a single vendor’s devices. To convert
a design from one vendor’s tools to another
is at best a time-consuming and errorprone
process, leaving the designer at the
mercy of the vendor in terms of the cost
and availability.
Vendor-independent tools provide a more
flexible alternative. Once the design is
captured, it can easily be retargeted from
one device family to another from the
same vendor, and can even be retargeted to
an entirely different family of FPGAs. Yet
another advantage of vendor-independent
flows involves the need to retarget the same
design to different silicon technologies.
Companies find that they can meet their
need for first silicon using FPGAs, and
then incorporate structured ASICs or
ASICs as they become available from
product lines. While vendor-supplied tools
provide IP that is only available for FPGA
devices, vendor-independent tools allow
designers to retarget the designs without
changing the golden design source.
7
Rule #7
Given the time, you can
always make a design better
– use design exploration.
Almost invariably, getting the functionality
of the design correct is just the beginning
– then begins the pursuit of improving
performance to make specs and trying
to shrink to a smaller device or go to a
slower speed grade to cut costs. Hardware
engineers have an arsenal of tools and
tricks at their disposal, but working at
gate-level – even at RTL level – has its
limits. Inserting intermediate registers
can be difficult. Optimizing quantization
throughout a design is particularly tedious
and error-prone when changing at the RTL
level. And, if the algorithm developer
comes up with a brilliant new idea two
weeks into the hardware design, chances
are that the project manager will decide to
stick with the old design rather than risk
the entire project schedule.
“To convert a design from
one vendor’s tools to
another is at best a
time-consuming and
error-prone process...”
The greatest benefits can be realized
by keeping the original floating-point
MATLAB source file as the golden source
for all design and using algorithmic
synthesis tools that synthesize from
MATLAB to RTL. Using architectural
synthesis tools such as AccelChip DSP
Synthesis, the algorithm designer can
make changes to the design well into
the flow, resynthesize to RTL, and work
with the hardware designer to determine
whether the design performance and
device utilization has improved. Possible
trade-offs given different levels of abstraction
are shown in Figure 3.
Figure 3
Wrapping up
Implementing DSP algorithms in silicon
used to be a task reserved for only the
most highly skilled and best equipped
design teams. The demand for a more
efficient path from algorithm to an ASIC
or FPGA has given rise to a new breed of
EDA companies, such as AccelChip, that
bridge the gap between DSP algorithm
development and silicon. Architectural
synthesis tools such as this accelerate
design and implementation by automatically
synthesizing algorithms written
in floating-point MATLAB model to
synthesizable VHDL or Verilog models
suitable for standard ASIC and FPGA
design flows. AccelChip’s toolset also
enables rapid design exploration targeting
fidelity, performance, area, and cost
tradeoffs for optimal results while using
MATLAB as a golden source.
Eric Cigan is the Product Marketing
Manager for AccelChip Inc., and is
responsible for product planning and
promotion for the AccelChip product
family. He has more than fourteen years’
experience in the EDA industry.
Reference:
1. Xilinx, June 2003.
2. Xilinx website.
For further information, contact Eric at:
AccelChip Inc.
1900 McCarthy Blvd., Suite 204
Milpitas, CA 95035
Tel: 408-943-0700 • Fax: 408-943-0661
E-mail: eric.cigan@accelchip.com
Website: www.accelchip.com
Embedded Computing Design Summer 2004 / 33