Intel 64 and IA-32 Architectures Software Developer's Manual

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Documentation Changes 3. Table on reserved bit checking has been corrected Table 3-5 of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A has been corrected. The corrections were to check bit values. The table is reproduced below. See the change bars for impacted lines. ------------------------------------------------------------------- Mode Paging Mode Paging Structure Check Bits 32-bit 4-KByte pages (PAE = 0, PSE = 0) PDE and PT No reserved bits checked 4-MByte page (PAE = 0, PSE = 1) PDE Bit [21] 4-KByte page (PAE = 0, PSE = 1) PDE No reserved bits checked 4-KByte and 4-MByte page (PAE = 0, PSE = 1) PTE No reserved bits checked 4-KByte and 2-MByte pages (PAE = 1, PSE = x) PDP table entry Bits [63:40] & [8:5] & [2:1] 2-MByte page (PAE = 1, PSE = x) PDE Bits [62:40] & [20:13] 4-KByte pages (PAE = 1, PSE = x) PDE Bits [62:40] 4-KByte pages (PAE = 1, PSE = x) PTE Bits [62:40] 64-bit 4-KByte and 2-MByte pages (PAE = 1, PSE = x) 4-KByte and 2-MByte pages (PAE = 1, PSE = x) PML4E Bits [51:40] PDPTE Bits [51:40] 2-MByte page (PAE = 1, PSE = x) PDE, 2-MByte page Bits [51:40] & [20:13] 4-KByte pages (PAE = 1, PSE = x) PDE, 4-KByte page Bits [51:40] 4-KByte pages (PAE = 1, PSE = x) PTE Bits [51:40] NOTE: x = Bit does not impact behavior. 4. MSR_THERM2_CTL description updated In Table B-2 of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, the description for MSR_THERM2_CTL(address 19DH) has been updated. The update targets Family F processors. See the table segment below. ------------------------------------------------------------------- Register Address Register Name Fields and Flags Model Availability Shared/ Unique Hex Dec Bit Description .... ... .... .... .... .... 19DH 413 IMSR_THERM2_CTL Thermal Monitor 2 Control. 3 Shared For Family F, Model 3 processors: When read, specifies the value of the target TM2 transition last written. When set, it sets the next target value for TM2 transition. 10 Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes
Documentation Changes Register Address Hex Dec Register Name Fields and Flags Model Availability Shared/ Unique Bit Description 4, 6 Shared For Family F, Model 4 and Model 6 processors: When read, specifies the value of the target TM2 transition last written. Writes may cause #GP exceptions. 5. Updated CPUID input format Some CPUID inputs require two input values. Documentation of the CPUID input format has been updated to reflect this requirement. See the summary table below (from Chapter 3, “CPUID—CPU Identification”, of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A). ------------------------------------------------------------------- CPUID—CPU Identification Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F A2 CPUID Valid Valid Returns processor identification and feature information to the EAX, EBX, ECX, and EDX registers, as determined by input entered in EAX (and, in some cases, ECX). .------------------------------------------------------------------- In addition, the input format is summarized in a figure located in the first chapter of each volume; this figure is reproduced below. ------------------------------------------------------------------- Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 11
Page 1 and 2: Intel ® 64 and IA-32 Architectures
Page 3 and 4: Contents Preface ..................
Page 5 and 6: Preface Preface This document is an
Page 7 and 8: Summary Table of Changes Summary Ta
Page 9: Documentation Changes
Page 13 and 14: Documentation Changes • Cores per
Page 15 and 16: Documentation Changes FI; bits are
Page 17 and 18: Documentation Changes • RFLAGS.
Page 19 and 20: Documentation Changes Opcode Instru
Page 21 and 22: Documentation Changes VAL (valid) f
Page 23 and 24: Documentation Changes Others may tr
Page 25 and 26: Documentation Changes If the source
Page 27 and 28: Documentation Changes THEN #SS(0);
Page 29 and 30: Documentation Changes END; THEN GOT
Page 31 and 32: Documentation Changes END; THEN GOT
Page 33 and 34: Documentation Changes VMMs should e
Page 35 and 36: Documentation Changes Bits in the i
Page 37 and 38: Documentation Changes 31(63) 13 12
Page 39 and 40: Documentation Changes SSE /SSE2/SSE
Page 41 and 42: Documentation Changes PAE MCE PGE P
Page 43 and 44: Documentation Changes Table 20-5. D
Page 45 and 46: Documentation Changes 2.5 CONTROL R
Page 47 and 48: Documentation Changes • The LOCK
Page 49 and 50: Documentation Changes Table 3-17. E
Page 51 and 52: Documentation Changes Note that, de
Page 53 and 54: Documentation Changes Description C
Page 55 and 56: Documentation Changes Flags Affecte
Page 57 and 58: Documentation Changes } If (Process
Page 59 and 60: Documentation Changes 18.3.1.1 Inst
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Documentation Changes • Reserved
Page 63 and 64:
Documentation Changes 41. Correctio
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Intel 64 and IA-32 Architectures Software Developer's Manual

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