Intel 64 and IA-32 Architectures Software Developer's Manual

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Documentation Changes 32. Entries added to CACHE-TLB table In Table 3-17 of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, entries have been added to the table. The table is reprinted below, see the change bars. • ------------------------------------------------------------------- Table 3-17. Encoding of Cache and TLB Descriptors Descriptor Value Cache or TLB Description 00H Null descriptor 01H Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries 02H Instruction TLB: 4 MByte pages, 4-way set associative, 2 entries 03H Data TLB: 4 KByte pages, 4-way set associative, 64 entries 04H Data TLB: 4 MByte pages, 4-way set associative, 8 entries 05H Data TLB1: 4 MByte pages, 4-way set associative, 32 entries 06H 1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size 08H 1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size 0AH 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size 0BH Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries 0CH 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size 22H 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector 23H 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector 25H 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector 29H 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector 2CH 1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size 30H 1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size 40H No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rdlevel cache 41H 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size 42H 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size 43H 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size 44H 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size 45H 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size 46H 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size 47H 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size 49H 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size 50H Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries 48 Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes
Documentation Changes Table 3-17. Encoding of Cache and TLB Descriptors (Continued) Descriptor Value Cache or TLB Description 51H 52H 56H 57H 5BH 5CH 5DH 60H 66H 67H 68H 70H 71H 72H 78H 79H 7AH 7BH 7CH 7DH 7FH 82H 83H 84H 85H 86H 87H B0H B3H B4H F0H F1H Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries Data TLB0: 4 MByte pages, 4-way set associative, 16 entries Data TLB0: 4 KByte pages, 4-way associative, 16 entries Data TLB: 4 KByte and 4 MByte pages, 64 entries Data TLB: 4 KByte and 4 MByte pages,128 entries Data TLB: 4 KByte and 4 MByte pages,256 entries 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size Trace cache: 12 K-μop, 8-way set associative Trace cache: 16 K-μop, 8-way set associative Trace cache: 32 K-μop, 8-way set associative 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries Data TLB: 4 KByte pages, 4-way set associative, 128 entries Data TLB1: 4 KByte pages, 4-way associative, 256 entries 64-Byte prefetching 128-Byte prefetching Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 49
Page 1 and 2: Intel ® 64 and IA-32 Architectures
Page 3 and 4: Contents Preface ..................
Page 5 and 6: Preface Preface This document is an
Page 7 and 8: Summary Table of Changes Summary Ta
Page 9 and 10: Documentation Changes
Page 11 and 12: Documentation Changes Register Addr
Page 13 and 14: Documentation Changes • Cores per
Page 15 and 16: Documentation Changes FI; bits are
Page 17 and 18: Documentation Changes • RFLAGS.
Page 19 and 20: Documentation Changes Opcode Instru
Page 21 and 22: Documentation Changes VAL (valid) f
Page 23 and 24: Documentation Changes Others may tr
Page 25 and 26: Documentation Changes If the source
Page 27 and 28: Documentation Changes THEN #SS(0);
Page 29 and 30: Documentation Changes END; THEN GOT
Page 31 and 32: Documentation Changes END; THEN GOT
Page 33 and 34: Documentation Changes VMMs should e
Page 35 and 36: Documentation Changes Bits in the i
Page 37 and 38: Documentation Changes 31(63) 13 12
Page 39 and 40: Documentation Changes SSE /SSE2/SSE
Page 41 and 42: Documentation Changes PAE MCE PGE P
Page 43 and 44: Documentation Changes Table 20-5. D
Page 45 and 46: Documentation Changes 2.5 CONTROL R
Page 47: Documentation Changes • The LOCK
Page 51 and 52: Documentation Changes Note that, de
Page 53 and 54: Documentation Changes Description C
Page 55 and 56: Documentation Changes Flags Affecte
Page 57 and 58: Documentation Changes } If (Process
Page 59 and 60: Documentation Changes 18.3.1.1 Inst
Page 61 and 62: Documentation Changes • Reserved
Page 63 and 64: Documentation Changes 41. Correctio

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