Intel 64 and IA-32 Architectures Software Developer's Manual

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Summary Table of Changes Summary Table of Changes The following table indicates documentation changes which apply to the IA-32 Intel ® architecture. This table uses the following notations: Codes Used in Summary Table Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document. Summary Table of Documentation Changes (Sheet 1 of 2) Number Documentation Changes 1 MOV—Move to/from Control Registers 2 XTPR Update Control information added 3 Table on reserved bit checking has been corrected 4 MSR_THERM2_CTL description updated 5 Updated CPUID input format 6 Flag information added for POPF/POPFD/POPFQ 7 Restriction added for total size field, microcode update format 8 Flag check corrected 9 REP/REPE/REPZ/REPNE/REPNZ summary table updated 10 Documentation of CMASK bit range corrected 11 Note defines additional restrictions on APIC DFR programming 12 Tables documenting MCA error codes updated 13 PUSHA/PUSHAD information updated 14 VMCALL pseudocode updated 15 Information on code fetches in uncacheable memory updated 16 PUSH description updated 17 IRET/IRETD pseudocode updated 18 BSR summary table updated 19 SYSCALL and SYSRET pseudocode updated 20 VMX Debug exceptions paragraph deleted 21 FLD list of exceptions updated 22 CPUID register reference corrected 23 UCOMISS range corrected in pseudocode 24 CR information updated 25 VMXON opcode corrected 26 MSR references updated 27 CR0.WP coverage updated 28 Illegal register address flag description updated 29 CPUID call reference corrected 30 Note describing semaphore restrictions added 6 Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes
Summary Table of Changes Summary Table of Documentation Changes (Sheet 2 of 2) Number Documentation Changes 31 DAS pseudocode updated 32 Entries added to CACHE-TLB table 33 Updated MOV to CR8 information 34 Information on ENTER instruction updated 35 Microcode update sections improved 36 Incorrect calls to CPUID.1:ECX[bit 9] have been corrected 37 String operation and EFLAGS.RF interactions clarified 38 MSR references corrected 39 Description of VM-entry checks on VM-execution control fields updated 40 STI, MOVSS/POPSS blocking behavior clarified 41 Correction for information on PEBS record size 42 Guest SMBASE entry added to table Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 7
Page 1 and 2: Intel ® 64 and IA-32 Architectures
Page 3 and 4: Contents Preface ..................
Page 5: Preface Preface This document is an
Page 9 and 10: Documentation Changes
Page 11 and 12: Documentation Changes Register Addr
Page 13 and 14: Documentation Changes • Cores per
Page 15 and 16: Documentation Changes FI; bits are
Page 17 and 18: Documentation Changes • RFLAGS.
Page 19 and 20: Documentation Changes Opcode Instru
Page 21 and 22: Documentation Changes VAL (valid) f
Page 23 and 24: Documentation Changes Others may tr
Page 25 and 26: Documentation Changes If the source
Page 27 and 28: Documentation Changes THEN #SS(0);
Page 29 and 30: Documentation Changes END; THEN GOT
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Page 33 and 34: Documentation Changes VMMs should e
Page 35 and 36: Documentation Changes Bits in the i
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Page 39 and 40: Documentation Changes SSE /SSE2/SSE
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Page 45 and 46: Documentation Changes 2.5 CONTROL R
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Page 53 and 54: Documentation Changes Description C
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Documentation Changes } If (Process
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Documentation Changes 18.3.1.1 Inst
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Documentation Changes • Reserved
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Documentation Changes 41. Correctio
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Intel 64 and IA-32 Architectures Software Developer's Manual

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