Intel 64 and IA-32 Architectures Software Developer's Manual

Documentation Changes
Compatibility Mode Exceptions
Same as for protected mode exceptions.
64-Bit Mode Exceptions
#GP(0)
#SS(U)
#PF(fault-code)
#AC(0)
If the memory address is in a non-canonical form.
If the stack address is in a non-canonical form.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory reference
is made while the current privilege level is
7. Restriction added for total size field, microcode update format
In Chapter 9 of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A, the total size field of the microcode update header must be in multiples of
1024 bytes (1 KBytes). This is now indicated in several locations. See the example
below.
-------------------------------------------------------------------
9.11.1 Microcode Update
. ... ....Text omitted here... ... ....
For microcode updates with a data size not equal to 00000000H, the total size field
specifies the size of the microcode update. The first 48 bytes contain the microcode
update header. The second part of the microcode update is the encrypted data. The data
size field of the microcode update header specifies the encrypted data size, its value
must be a multiple of the size of DWORD. The total size field of the microcode
update header specifies the encrypted data size plus the header size; its value
must be in multiples of 1024 bytes (1 KBytes). The optional extended signature
table if implemented follows the encrypted data, and its size is calculated by (Total Size
– (Data Size + 48)).
.. ... ....Text omitted here... ... ....
8. Flag check corrected
In Section 22.3.4 of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B), a flag check was incorrectly indicated in the following section. The section is
reproduced below, with the correction.
-------------------------------------------------------------------
22.3.1.4 Checks on Guest RIP and RFLAGS
The following checks are performed on fields in the guest-state area corresponding to
RIP and RFLAGS:
• RIP. The following checks are performed on processors that support Intel 64
Technology:
— Bits 63:32 must be 0 if the “IA-32e mode guest” VM-entry control is 0 or if the L
bit (bit 13) in the access-rights field for CS is 0.
— If the processor supports N < 64 linear-address bits, bits 63:N must be identical
if the “IA-32e mode guest” VM-entry control is 1 and the L bit in the access-rights
field for CS is 1. 1 (No check applies if the processor supports 64 linear-address
bits.)
16 Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes