Intel 64 and IA-32 Architectures Software Developer's Manual

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Documentation Changes Documentation Changes 1. MOV—Move to/from Control Registers In Chapter 3, “MOV—Move to/from Control Registers” of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A; the summary table has been corrected. The updated table is reproduced below. Change bars mark corrected lines. ------------------------------------------------------------------- Opcode Instruction 64-Bit Mode Compat/ Leg Mode Description 0F 22 /r MOV CR0,r32 N.E. Valid Move r32 to CR0. 0F 22 /r MOV CR0,r64 Valid N.E. Move r64 to extended CR0. 0F 22 /r MOV CR2,r32 N.E. Valid Move r32 to CR2. 0F 22 /r MOV CR2,r64 Valid N.E. Move r64 to extended CR2. 0F 22 /r MOV CR3,r32 N.E. Valid Move r32 to CR3. 0F 22 /r MOV CR3,r64 Valid N.E. Move r64 to extended CR3. 0F 22 /r MOV CR4,r32 N.E. Valid Move r32 to CR4. 0F 22 /r MOV CR4,r64 Valid N.E. Move r64 to extended CR4. 0F 20 /r MOV r32,CR0 N.E. Valid Move CR0 to r32. 0F 20 /r MOV r64,CR0 Valid N.E. Move extended CR0 to r64. 0F 20 /r MOV r32,CR2 N.E. Valid Move CR2 to r32. 0F 20 /r MOV r64,CR2 Valid N.E. Move extended CR2 to r64. 0F 20 /r MOV r32,CR3 N.E. Valid Move CR3 to r32. 0F 20 /r MOV r64,CR3 Valid N.E. Move extended CR3 to r64. 0F 20 /r MOV r32,CR4 N.E. Valid Move CR4 to r32. 0F 20 /r MOV r64,CR4 Valid N.E. Move extended CR4 to r64. 0F 20 /r MOV r32,CR8 N.E. N.E. Move CR8 to r32. REX + 0F 20 /r MOV r64,CR8 Valid N.E. Move extended CR8 to r64. 1 NOTE: 1. MOV CR* instructions, except for MOV CR8, are serializing instructions. MOV CR8 is not architecturally defined as a serializing instruction. For more information, see Chapter 7 in Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. 2. XTPR Update Control information added Figure 3-6 and Table 3-15 in Chapter 3, “CPUID—CPU Identification” of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, information on the CPUID xTPR update control bit has been added. The information is reproduced below. ------------------------------------------------------------------- 8 Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes
Documentation Changes Figure 3-6. Extended Feature Information Returned in the ECX Register Table 3-15. More on Extended Feature Information Returned in the ECX Register Bit # Mnemonic Description .... .... .....[not all lines in table are shown] 13 CMPXCHG16B CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the “CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes” section in this chapter for a description. 14 xTPR Update Control 31 - 15 Reserved Reserved xTPR Update Control. A value of 1 indicates that the processor supports changing IA32_MISC_ENABLES[bit 23]. ------------------------------------------------------------------- Information on the CPUID xTPR update control function has also been added to the discussions of IA32_MISC_ENABLES[bit 23] in Appendix B (Tables B-1, B-2, B-5) of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B. The added information is reproduced below. ------------------------------------------------------------------- Register Address Hex Dec Register Name Fields and Flags Model Availability Shared/ Unique Bit Description 23 xTPR Message Disable (R/W). When set to 1, xTPR messages are disabled. xTPR messages are optional messages that allow the processor to inform the chipset of its priority. The default is processor specific. Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 9
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Intel 64 and IA-32 Architectures Software Developer's Manual

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