Intel 64 and IA-32 Architectures Software Developer's Manual

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL ® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I 2 C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I 2 C bus/protocol and was developed by Intel. Implementations of the I 2 C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel, Pentium, Celeron, Intel SpeedStep, Intel Xeon, Intel 64, and the Intel logo, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2002–2006, Intel Corporation. All rights reserved. 2 Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes
Contents Preface ............................................................................................... 5 Summary Table of Changes ................................................................... 6 Documentation Changes ........................................................................ 8 Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 3
Page 1: Intel ® 64 and IA-32 Architectures
Page 5 and 6: Preface Preface This document is an
Page 7 and 8: Summary Table of Changes Summary Ta
Page 9 and 10: Documentation Changes
Page 11 and 12: Documentation Changes Register Addr
Page 13 and 14: Documentation Changes • Cores per
Page 15 and 16: Documentation Changes FI; bits are
Page 17 and 18: Documentation Changes • RFLAGS.
Page 19 and 20: Documentation Changes Opcode Instru
Page 21 and 22: Documentation Changes VAL (valid) f
Page 23 and 24: Documentation Changes Others may tr
Page 25 and 26: Documentation Changes If the source
Page 27 and 28: Documentation Changes THEN #SS(0);
Page 29 and 30: Documentation Changes END; THEN GOT
Page 31 and 32: Documentation Changes END; THEN GOT
Page 33 and 34: Documentation Changes VMMs should e
Page 35 and 36: Documentation Changes Bits in the i
Page 37 and 38: Documentation Changes 31(63) 13 12
Page 39 and 40: Documentation Changes SSE /SSE2/SSE
Page 41 and 42: Documentation Changes PAE MCE PGE P
Page 43 and 44: Documentation Changes Table 20-5. D
Page 45 and 46: Documentation Changes 2.5 CONTROL R
Page 47 and 48: Documentation Changes • The LOCK
Page 49 and 50: Documentation Changes Table 3-17. E
Page 51 and 52: Documentation Changes Note that, de
Page 53 and 54:
Documentation Changes Description C
Page 55 and 56:
Documentation Changes Flags Affecte
Page 57 and 58:
Documentation Changes } If (Process
Page 59 and 60:
Documentation Changes 18.3.1.1 Inst
Page 61 and 62:
Documentation Changes • Reserved
Page 63 and 64:
Documentation Changes 41. Correctio
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Intel 64 and IA-32 Architectures Software Developer's Manual

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