Intel 64 and IA-32 Architectures Software Developer's Manual

Documentation Changes
Table 14-16. IA32_MCi_Status [15:0] Compound Error Code Encoding
Type Form Interpretation
Generic Memory
Hierarchy
000F 0000 0000 11LL
Generic memory hierarchy error
TLB Errors 000F 0000 0001 TTLL {TT}TLB{LL}_ERR
Memory Hierarchy Errors 000F 0001 RRRR TTLL {TT}CACHE{LL}_{RRRR}_ERR
Bus and Interconnect
Errors
000F 1PPT RRRR IILL
BUS{LL}_{PP}_{RRRR}_{II}_{T}_ERR
The “Interpretation” column in the table indicates the name of a compound error. The
name is constructed by substituting mnemonics for the sub-field names given within
curly braces. For example, the error code ICACHEL1_RD_ERR is constructed from the
form:
{TT}CACHE{LL}_{RRRR}_ERR,
where {TT} is replaced by I, {LL} is replaced by L1, and {RRRR} is replaced by RD.
For more information on the “Form” and “Interpretation” columns, see Section 14.7.2.1,
“Correction Report Filtering (F) Bit” through Section 14.7.2.5, “Bus and Interconnect
Errors”.
.. ... ....Text omitted here... ... ....
13. PUSHA/PUSHAD information updated
In the Description subsection, “PUSHA/PUSHAD—Push All General-Purpose Registers”, in
Chapter 4 of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B, the language has been updated to correct an error (EBP was listed twice in
the earlier version). See the change bar and bold text.
-------------------------------------------------------------------
PUSHA/PUSHAD—Push All General-Purpose Registers
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
60 PUSHA Invalid Valid Push AX, CX, DX, BX, original SP, BP, SI,
and DI.
60 PUSHAD Invalid Valid Push EAX, ECX, EDX, EBX, original ESP,
EBP, ESI, and EDI.
Description
Pushes the contents of the general-purpose registers onto the stack. The registers are
stored on the stack in the following order: EAX, ECX, EDX, EBX, ESP (original
value), EBP, ESI, and EDI (if the current operand-size attribute is 32) and AX,
CX, DX, BX, SP (original value), BP, SI, and DI (if the operand-size attribute is
16). These instructions perform the reverse operation of the POPA/POPAD instructions.
The value pushed for the ESP or SP register is its value before prior to pushing the first
register (see the “Operation” section below).
The PUSHA (push all) and PUSHAD (push all double) mnemonics reference the same
opcode. The PUSHA instruction is intended for use when the operand-size attribute is 16
and the PUSHAD instruction for when the operand-size attribute is 32. Some assemblers
may force the operand size to 16 when PUSHA is used and to 32 when PUSHAD is used.
22 Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes