Intel 64 and IA-32 Architectures Software Developer's Manual

Documentation Changes
FI;
FI;
read SMM-monitor features field in MSEG (see Section 24.16.6.2,
in the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B);
IF features field is invalid
THEN
leave SMM;
VMfailValid(VMCALL with invalid SMM-monitor features);
ELSE activate dual-monitor treatment of SMIs and SMM (see Section 24.16.6
in the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B);
FI;
15. Information on code fetches in uncacheable memory updated
In Section 10.3.3 of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A, the language has been updated to address confusion.
The section is reproduced below.
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10.3.3 Code Fetches in Uncacheable Memory
Programs may execute code from uncacheable (UC) memory, but the implications are
different from accessing data in UC memory. When doing code fetches, the processor
never transitions from cacheable code to UC code speculatively. It also never
speculatively fetches branch targets that result in UC code.
The processor may fetch the same UC cache line multiple times in order to decode an
instruction once. It may decode consecutive UC instructions in a cacheline without
fetching between each instruction. It may also fetch additional cachelines from the same
or a consecutive 4-KByte page in order to decode one non-speculative UC instruction
(this can be true even when the instruction is contained fully in one line).
Because of the above and because cacheline sizes may change in future processors,
software should avoid placing memory-mapped I/O with read side effects in the same
page or in a subsequent page used to execute UC code.
16. PUSH description updated
In the Description subsection, “PUSH—Push Word, Doubleword or Quadword Onto the
Stack”, in Chapter 4 of the Intel ® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2B, the language describing the instructions in real-address mode has
been corrected.
The subsection is reprinted below. See the change bar.
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Description
Decrements the stack pointer and then stores the source operand on the top of the
stack. The address-size attribute of the stack segment determines the stack pointer size
(16, 32 or 64 bits). The operand-size attribute of the current code segment determines
the amount the stack pointer is decremented (2, 4 or 8 bytes).
In non-64-bit modes: if the address-size and operand-size attributes are 32, the 32-bit
ESP register (stack pointer) is decremented by 4. If both attributes are 16, the 16-bit SP
register (stack pointer) is decremented by 2.
24 Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes