Intel 64 and IA-32 Architectures Software Developer's Manual

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Documentation Changes RETURN-TO-VIRTUAL-8086-MODE: (* Interrupted procedure was in virtual-8086 mode: PE = 1, VM = 1 in flag image *) IF top 24 bytes of stack are not within stack segment limits THEN #SS(0); FI; IF instruction pointer not within code segment limits THEN #GP(0); FI; CS ← tempCS; EIP ← tempEIP; EFLAGS ← tempEFLAGS; TempESP ← Pop(); TempSS ← Pop(); ES ← Pop(); (* Pop 2 words; throw away high-order word *) DS ← Pop(); (* Pop 2 words; throw away high-order word *) FS ← Pop(); (* Pop 2 words; throw away high-order word *) GS ← Pop(); (* Pop 2 words; throw away high-order word *) SS:ESP ← TempSS:TempESP; CPL ← 3; (* Resume execution in Virtual-8086 mode *) END; TASK-RETURN: (* PE = 1, VM = 0, NT = 1 *) Read segment selector in link field of current TSS; IF local/global bit is set to local or index not within GDT limits THEN #TS (TSS selector); FI; Access TSS for task specified in link field of current TSS; IF TSS descriptor type is not TSS or if the TSS is marked not busy THEN #TS (TSS selector); FI; IF TSS not present THEN #NP(TSS selector); FI; SWITCH-TASKS (without nesting) to TSS specified in link field of current TSS; Mark the task just abandoned as NOT BUSY; IF EIP is not within code segment limit THEN #GP(0); FI; END; PROTECTED-MODE-RETURN: (* PE = 1, VM = 0 in flags image *) IF return code segment selector is NULL THEN GP(0); FI; IF return code segment selector addrsses descriptor beyond descriptor table limit THEN GP(selector); FI; Read segment descriptor pointed to by the return code segment selector; IF return code segment descriptor is not a code segment THEN #GP(selector); FI; IF return code segment selector RPL < CPL THEN #GP(selector); FI; IF return code segment descriptor is conforming and return code segment DPL > return code segment selector RPL THEN #GP(selector); FI; IF return code segment descriptor is not present THEN #NP(selector); FI; IF return code segment selector RPL > CPL 28 Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes
Documentation Changes END; THEN GOTO RETURN-OUTER-PRIVILEGE-LEVEL; ELSE GOTO RETURN-TO-SAME-PRIVILEGE-LEVEL; FI; RETURN-TO-SAME-PRIVILEGE-LEVEL: (* PE = 1, VM = 0 in flags image, RPL = CPL *) IF new mode ≠ 64-Bit Mode THEN IF tempEIP is not within code segment limits THEN #GP(0); FI; EIP ← tempEIP; ELSE (* new mode = 64-bit mode *) IF tempRIP is non-canonical THEN #GP(0); FI; RIP ← tempRIP; FI; CS ← tempCS; (* Segment descriptor information also loaded *) EFLAGS (CF, PF, AF, ZF, SF, TF, DF, OF, NT) ← tempEFLAGS; IF OperandSize = 32 or OperandSize = 64 THEN EFLAGS(RF, AC, ID) ← tempEFLAGS; FI; IF CPL ≤ IOPL THEN EFLAGS(IF) ← tempEFLAGS; FI; IF CPL = 0 THEN EFLAGS(IOPL) ← tempEFLAGS; IF OperandSize = 32 THEN EFLAGS(VM, VIF, VIP) ← tempEFLAGS; FI; IF OperandSize = 64 THEN EFLAGS( VIF, VIP) ← tempEFLAGS; FI; FI; END; RETURN-TO-OUTER-PRIVILEGE-LEVEL: IF OperandSize = 32 THEN IF top 8 bytes on stack are not within limits THEN #SS(0); FI; ELSE (* OperandSize = 16 *) IF top 4 bytes on stack are not within limits THEN #SS(0); FI; FI; Read return segment selector; IF stack segment selector is NULL THEN #GP(0); FI; IF return stack segment selector index is not within its descriptor table limits THEN #GP(SSselector); FI; Read segment descriptor pointed to by return segment selector; IF stack segment selector RPL ≠ RPL of the return code segment selector or the stack segment descriptor does not indicate a a writable data segment; or the stack segment DPL ≠ RPL of the return code segment selector THEN #GP(SS selector); FI; IF stack segment is not present THEN #SS(SS selector); FI; IF new mode ≠ 64-Bit Mode Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 29
Page 1 and 2: Intel ® 64 and IA-32 Architectures
Page 3 and 4: Contents Preface ..................
Page 5 and 6: Preface Preface This document is an
Page 7 and 8: Summary Table of Changes Summary Ta
Page 9 and 10: Documentation Changes
Page 11 and 12: Documentation Changes Register Addr
Page 13 and 14: Documentation Changes • Cores per
Page 15 and 16: Documentation Changes FI; bits are
Page 17 and 18: Documentation Changes • RFLAGS.
Page 19 and 20: Documentation Changes Opcode Instru
Page 21 and 22: Documentation Changes VAL (valid) f
Page 23 and 24: Documentation Changes Others may tr
Page 25 and 26: Documentation Changes If the source
Page 27: Documentation Changes THEN #SS(0);
Page 31 and 32: Documentation Changes END; THEN GOT
Page 33 and 34: Documentation Changes VMMs should e
Page 35 and 36: Documentation Changes Bits in the i
Page 37 and 38: Documentation Changes 31(63) 13 12
Page 39 and 40: Documentation Changes SSE /SSE2/SSE
Page 41 and 42: Documentation Changes PAE MCE PGE P
Page 43 and 44: Documentation Changes Table 20-5. D
Page 45 and 46: Documentation Changes 2.5 CONTROL R
Page 47 and 48: Documentation Changes • The LOCK
Page 49 and 50: Documentation Changes Table 3-17. E
Page 51 and 52: Documentation Changes Note that, de
Page 53 and 54: Documentation Changes Description C
Page 55 and 56: Documentation Changes Flags Affecte
Page 57 and 58: Documentation Changes } If (Process
Page 59 and 60: Documentation Changes 18.3.1.1 Inst
Page 61 and 62: Documentation Changes • Reserved
Page 63 and 64: Documentation Changes 41. Correctio

Intel 64 and IA-32 Architectures Software Developer's Manual

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