Intel 64 and IA-32 Architectures Software Developer's Manual

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Documentation Changes FLAG Send Checksum Error Receive Checksum Error Send Illegal Vector Receive Illegal Vector Illegal Reg. Address Function (P6 family and Pentium processors only) Set when the local APIC detects a checksum error for a message that it sent on the APIC bus. (P6 family and Pentium processors only) Set when the local APIC detects a checksum error for a message that it received on the APIC bus. Set when the local APIC detects an illegal vector in the message that it is sending. Set when the local APIC detects an illegal vector in the message it received, including an illegal vector code in the local vector table interrupts or in a self-interrupt. (Pentium 4, Intel Xeon, and P6 family processors only) Set when the processor is trying to access a register in the processor's local APIC register address space that is reserved (see Table 8-1). Addresses in one the 0x10 byte regions marked reserved are illegal register addresses. The Local APIC Register Map is the address range of the APIC register base address (specified in the IA32_APIC_BASE MSR) plus 4 KBytes. 29. CPUID call reference corrected In Section 3.3.1 of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, a CPUID reference has been corrected. See the change bar and the bold text. ------------------------------------------------------------------- 3.3.1 Physical Address Space for Processors with Intel ® 64 Technology On processors that support Intel 64 Technology (CPUID.80000001:EDX[29] = 1), the size of the physical address range is implementation-specific and indicated by CPUID.80000008H:EAX[bits 7-0]. For the format of information returned in EAX, see “CPUID—CPU Identification” in Chapter 3 of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A. 30. Note describing semaphore restrictions added In Section 7.1.2.2 of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, the language has been added to clarify a usage restriction. See the change bar below. ------------------------------------------------------------------- 7.1.2.2 Software Controlled Bus Locking To explicitly force the LOCK semantics, software can use the LOCK prefix with the following instructions when they are used to modify a memory location. An invalidopcode exception (#UD) is generated when the LOCK prefix is used with any other instruction or when no write operation is made to memory (that is, when the destination operand is in a register). • The bit test and modify instructions (BTS, BTR, and BTC). • The exchange instructions (XADD, CMPXCHG, and CMPXCHG8B). 46 Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes
Documentation Changes • The LOCK prefix is automatically assumed for XCHG instruction. • The following single-operand arithmetic and logical instructions: INC, DEC, NOT, and NEG. • The following two-operand arithmetic and logical instructions: ADD, ADC, SUB, SBB, AND, OR, and XOR. A locked instruction is guaranteed to lock only the area of memory defined by the destination operand, but may be interpreted by the system as a lock for a larger memory area. Software should access semaphores (shared memory used for signalling between multiple processors) using identical addresses and operand lengths. For example, if one processor accesses a semaphore using a word access, other processors should not access the semaphore using a byte access. NOTE Do not implement semaphores using the WC memory type. Do not perform non-temporal stores to a cache line containing a location used to implement a semaphore. .. ... ....Text omitted here... ... .... 31. DAS pseudocode updated In Chapter 3, “DAS—Decimal Adjust AL after Subtraction”, of the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, the pseudocode has been corrected. See the change bar below. ------------------------------------------------------------------- Operation IF 64-Bit Mode THEN #UD; ELSE old_AL ← AL; old_CF ← CF; CF ← 0; IF (((AL AND 0FH) > 9) or AF = 1) THEN AL ← AL − 6; CF ← old_CF or (Borrow from AL ← AL − 6); AF ← 1; ELSE AF ← 0; FI; IF ((old_AL > 99H) or (old_CF = 1)) THEN AL ← AL − 60H; CF ← 1; FI; FI; Intel ® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 47
Page 1 and 2: Intel ® 64 and IA-32 Architectures
Page 3 and 4: Contents Preface ..................
Page 5 and 6: Preface Preface This document is an
Page 7 and 8: Summary Table of Changes Summary Ta
Page 9 and 10: Documentation Changes
Page 11 and 12: Documentation Changes Register Addr
Page 13 and 14: Documentation Changes • Cores per
Page 15 and 16: Documentation Changes FI; bits are
Page 17 and 18: Documentation Changes • RFLAGS.
Page 19 and 20: Documentation Changes Opcode Instru
Page 21 and 22: Documentation Changes VAL (valid) f
Page 23 and 24: Documentation Changes Others may tr
Page 25 and 26: Documentation Changes If the source
Page 27 and 28: Documentation Changes THEN #SS(0);
Page 29 and 30: Documentation Changes END; THEN GOT
Page 31 and 32: Documentation Changes END; THEN GOT
Page 33 and 34: Documentation Changes VMMs should e
Page 35 and 36: Documentation Changes Bits in the i
Page 37 and 38: Documentation Changes 31(63) 13 12
Page 39 and 40: Documentation Changes SSE /SSE2/SSE
Page 41 and 42: Documentation Changes PAE MCE PGE P
Page 43 and 44: Documentation Changes Table 20-5. D
Page 45: Documentation Changes 2.5 CONTROL R
Page 49 and 50: Documentation Changes Table 3-17. E
Page 51 and 52: Documentation Changes Note that, de
Page 53 and 54: Documentation Changes Description C
Page 55 and 56: Documentation Changes Flags Affecte
Page 57 and 58: Documentation Changes } If (Process
Page 59 and 60: Documentation Changes 18.3.1.1 Inst
Page 61 and 62: Documentation Changes • Reserved
Page 63 and 64: Documentation Changes 41. Correctio

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