FS4400 PCI Express State Analysis Probe User Manual - FuturePlus ...

Lane 4 10 Logical Lane 4 Data
(x8 mode only)
Bit 9 is Invalid flag, Bit 8 is Control
flag
Lane 5 10 Logical Lane 5 Data
(x8 mode only)
Bit 9 is Invalid flag, Bit 8 is Control
flag
Lane 6 10 Logical Lane 6 Data
(x8 mode only)
Bit 9 is Invalid flag, Bit 8 is Control
flag
Lane 7 10 Logical Lane 7 Data
(x8 mode only)
Bit 9 is Invalid flag, Bit 8 is Control
flag
NA
NA
NA
NA
B3[11:2]
B3[1:0],
B2[16:9]
B2[8:0],
B1[15]
B1[14:5]
Additional Bits
(PCIe)
The FS4400 generates a number of identification and control bits that are used by the
Protocol Decoder and logic analyzer. There are a few that don’t have pre-defined
labels, (other than being in the VAB label used by the Inverse Assembler).
These are also available to the user and can be used as described below.
Functional Name
No. of
Bits
Definition/Usage
ALIGNED 1 1 = multi-lane link is aligned
0 = lane deskew has failed
DATA PRESENT
[3,2,1,0]
LOS
[3,2,1,0]
4 (Exists in x1 x2 x4 mode only.)
1 = Lane data is present.
0 = Lane data is not present due to effects
of spreading x1 or x2 data across 4 lanes.
4 Lane-by Lane LOS bits.
(Provided in x1 x2 x4 mode only.)
1 = Loss of Signal in Lane
0 = Signal Detected or Lane not used
Any LOS 1 Composite LOS bit (all active lanes)
(Provided in x8 mode only.)
Logic
Analyzer
Pod
In x1 x2 x4
mode
A4[14]
A3[14:11]
A3[10:7]
NA
Logic
Analyzer
Pod
In x8 mode
B4[9]
NA
NA
B3[12]
40