FS4400 PCI Express State Analysis Probe User Manual - FuturePlus ...

Observing PCIe Link Activity in ASPM :
PCI-Express Active State Power Management (ASPM) protocol, allows links to
transition back and forth between active (L0) and low power states (L0s, L1, L2 etc).
The probe will follow links that go up and down:
• When a link is constantly transitioning back and forth between active and low
power states, the Signal LEDs and the log file will report errors that can be
ignored.
• The probe can follow Fast Training. If a link is transitioning between active (L0)
and shallow power saving (L0s), the probe will achieve very low N_FTS when
operated in ASPM mode, selected by clicking the “ASPM” checkbox on the
Config window before running the probe. This mode allows the probe to start
capturing data early during the Fast Training ordered sets.
Finding Stable PCIe Link Activity:
When a link is expected to perform initialization, set the analyzer to trigger on:
• “Event Code = TS2 training set”
This assures the link is up and running because a PCIe device issues TS2 ordered sets
only after it has received valid TS1 ordered sets from the other direction.
Finding Link Startup During Fast Training:
When a link is expected to perform fast training, set the analyzer to trigger on:
• “Event Code = FTS Ordered Set”
Finding the Start of Signal Activity:
Set the analyzer to trigger on:
• “Event Code = Link Alive”
Another method is to trigger based on signal detection status (LOS = loss of signal).
Note this method can only be used when the probe is not setup for ASPM mode:
• “Event Code = Beacon” (signal detected on lane 0)
• LOS[0] goes low (for 1-lane operation)
• LOS[1:0] goes low (all lanes signal detected in 2-lane operation)
• LOS[3:0] goes low (all lanes signal detected in 4-lane operation)
• ANYLOS goes low (all lanes signal detected in 8-lane operation)
Note: Some links startup cleanly (within 300 nS of de-assertion of LOS flag), but others
do not. The probe itself can not achieve lock quickly until it receives a stable signal and
a stable reference clock. Signal detection does not imply a valid serial data signal.
Signal detection (LOS status) is delayed relative to link data capture.
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