PCI8280 Telecom PCI Module Technical Reference Manual ... - NAT
PCI8280 Telecom PCI Module Technical Reference Manual ... - NAT
PCI8280 Telecom PCI Module Technical Reference Manual ... - NAT
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3.4.3 H.100 Bus Compatibility<br />
<strong><strong>PCI</strong>8280</strong> – <strong>Technical</strong> <strong>Reference</strong> <strong>Manual</strong><br />
The H.100 bus implemented on the <strong><strong>PCI</strong>8280</strong> may be used to interconnect with other boards in<br />
the system either supporting H.100 or SCbus. SCbus data lines correspond to H.100 data lines<br />
CT_D0 – 15. See chapters 5.8 and 5.9 (H.100 connectors) for reference.<br />
3.4.4 E1/T1/J1 Line Interfaces<br />
The four E1/T1/J1 interfaces connect the Infineon QuadFALC framer to the front panel RJ45<br />
connector S1. Timing and interface characteristics can be set up by software within the<br />
QuadFALC, the correct line impedance is selected by programming the IMPSELA to<br />
IMPSELC port signals as described below in chapter 4.2.1.1. The line interfaces conform to<br />
EN60950 and G.703.<br />
3.5 Ethernet<br />
The LXT972 Ethernet LIU is connected to the MPC8280 through the MII interface. It<br />
connects to the front panel connector S3.<br />
Configuration settings of the LXT972 are done by MPC8280 port pins. This applies to signals<br />
TxSLEWx, PAUSE, and PWRDWN. Refer to Table 8: for details. ADDR0 is grounded.<br />
Version 1.2 © N.A.T. GmbH 19
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