PCI8280 Telecom PCI Module Technical Reference Manual ... - NAT

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PCI8280 – Technical Reference Manual 6.3 Recommended Register Setup of the Memory Controller: 6.3.1 Base Registers BRx: The base addresses given in the description below are the ones chosen for the OK1 and VxWorks implementations for the NPMC-8280-E1/T1/J1. They may be altered to suit the user’s needs. BRx: Base Register of the corresponding CS; CS settings as described in Table 4: above. BR0 Bit Name Value Description Bit 0-16 BA base address , FLASH Bit 17-18 rsvd 0b clear Bit 19-20 PS 10b port size 16 bit Bit 21-22 DECC 0b ECC disabled Bit 23 WP 0b R/W Bit 24-26 MS 0b default, 601 bus Bit 27 EMEMC 0b memory controller active Bit 28-29 ATOM 0b no atomic operations Bit 30 DR 0b no data pipelining Bit 31 V 1b valid bank BR1 not used. BR2 Bit Name Value Description Bit 0-16 BA base address , SDRAM CS0 Bit 17-18 rsvd 0b clear Bit 19-20 PS 0b port size 64 bit Bit 21-22 DECC 0b ECC disabled Bit 23 WP 0b R/W Bit 24-26 MS 010b SDRAM, 601 bus Bit 27 EMEMC 0b memory controller active Bit 28-29 ATOM 0b no atomic operations Bit 30 DR 0b no data pipelining Bit 31 V 1b valid bank The settings of BR2 and BR3 are suitable for the default 32 MB SODIMM module installed. The default module uses only one CS, hence the programming of BR3/OR3 is not necessary. Version 1.2 © N.A.T. GmbH 42
PCI8280 – Technical Reference Manual BR3 Bit Name Value Description Bit 0-16 BA base address , SDRAM CS1 Bit 17-18 rsvd 0b clear Bit 19-20 PS 0b port size 64 bit Bit 21-22 DECC 0b ECC disabled Bit 23 WP 0b R/W Bit 24-26 MS 010b SDRAM, 601 bus Bit 27 EMEMC 0b memory controller active Bit 28-29 ATOM 0b no atomic operations Bit 30 DR 0b no data pipelining Bit 31 V 0b invalid bank BR4 Bit Name Value Description Bit 0-16 BA base address , Reset register Bit 17-18 rsvd 0b clear Bit 19-20 PS 01b port size 8 bit Bit 21-22 DECC 0b ECC disabled Bit 23 WP 0b R/W Bit 24-26 MS 0b GPCM, 601 bus Bit 27 EMEMC 0b memory controller active Bit 28-29 ATOM 0b no atomic operations Bit 30 DR 0b no data pipelining Bit 31 V 1b valid bank BR5 Bit Name Value Description Bit 0-16 BA base address , TSI Bit 17-18 rsvd 0b clear Bit 19-20 PS 01b port size 8 bit Bit 21-22 DECC 0b ECC disabled Bit 23 WP 0b R/W Bit 24-26 MS 0b GPCM, 601 bus Bit 27 EMEMC 0b memory controller active Bit 28-29 ATOM 0b no atomic operations Bit 30 DR 0b no data pipelining Bit 31 V 1b valid bank Version 1.2 © N.A.T. GmbH 43
Page 1 and 2: PCI8280 - Technical Reference Manua
Page 7 and 8: Conventions PCI8280 - Technical Ref
Page 9 and 10: 1.1 Board Features • CPU PCI8280
Page 11 and 12: 2 Installation 2.1 Safety Note CAUT
Page 13 and 14: 2.3 Location Overview PCI8280 - Tec
Page 15 and 16: 3.3 Memory 3.3.1 SDRAM PCI8280 - Te
Page 19 and 20: 3.4.3 H.100 Bus Compatibility PCI82
Page 25 and 26: 4.2.1 Signal Description PCI8280 -
Page 27 and 28: 4.2.1.8 SDRAM Configuration Pins PC
Page 29 and 30: 4.5 Register 4.5.1 PCB Revision Reg
Page 31 and 32: 5 Connectors 5.1 Connector Overview
Page 41: PCI8280 - Technical Reference Manua
Page 45 and 46: 6.3.2 Option Registers ORx PCI8280

PCI8280 Telecom PCI Module Technical Reference Manual ... - NAT

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