PCI8280 Telecom PCI Module Technical Reference Manual ... - NAT

PCI8280 – Technical Reference Manual
6.2 Recommended General Control Register Setup
6.2.1 Register-Setup of the System Clock Control Register (SCCR)
SCCR Bit Name Value Description
Bit 0-28 rsvd 0b clear
Bit 29 CLPD 0b CPM does not enter low power mode
Bit 30-31 DFBRG 0b division factor of 4
6.2.2 Register-Setup of the System Protection Control Register (SYPCR)
SYPCR Bit Name Value Description
Bit 0-15 SWTC 0xFFFF software watchdog timer count
Bit 16-23 BMT 0xFF bus monitor timing
Bit 24 PBME 1b 60x bus monitor enabled
Bit 25 LBME 1b local bus monitor enabled
Bit 26-28 rsvd 0b clear
Bit 29 SWE 0b software watchdog disabled
Bit 30 SWRI 1b watchdog and bus monitors cause soft reset
Bit 31 SWP 1b software watchdog timer is prescaled
6.2.3 Register-Setup of the Bus Configurations Register (BCR)
BCR Bit Name Value Description
Bit 0 EBM 1b external bus mode 60x mode
Bit 1-3 APD 100b address phase delay
Bit 4 L2C 0b no secondary cache
Bit 5-7 L2D 0b hit delay, not applicable
Bit 8 PLDP 1b pipeline max. depth
Bit 9-10 rsvd 0b clear
Bit 11 EAV 1b full address on 60x bus
Bit 12 ETM 0b compatibility mode enable, disabled
Bit 13 LETM 0b local compatibility mode enable, disabled
Bit 14 EPAR 0b even parity
Bit 15 LEPAR 0b local even parity
Bit 16-18 NPQM 111b non PowerQUICC master
Bit 19-20 rsvd 0b clear
Bit 21 EXDD 0b external master delay enabled
Bit 22-26 rsvd 0b clear
Bit 27 ISPS 0b internal space port size is 64 bit
Bit 28-31 rsvd 0b clear
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