A formal description of SYSTEM/360

memoly accessoperationmemoly accesspriorityThe MAC operation, which occurs in the instruction fetch andthroughout the EXC operation, serves to fetch from or storein memory a specified number of bytes beginning at a specifiedaddress. Because it incorporates certain tests and other functions,it warrants a detailed scrutiny.The general form of the MAC operation is MACi (j; k), wherei specifies one of nine identical but independent MAC programs,i = 9 for the CPU memory-access, i = 8 for the interval timer,and i = 0-6 for the channels; where k is the vector involvedin the transfer to or from memory; and where j is a four-componentvector specifying the address in memory (jo), the numberof bytes transferred (jl), the performance of a fetch (j, = f)or store (j2 = s), and the type of address being treated (j3 = dfor data address, i for instruction address, g for a machinegenerated[;.e., fixed] address, and h for hold, which preventsany of the other MAC’ programs from operating until the currentMACi program has been used again with j, # h).Since the several MAC’ programs all use the same memory,they must observe a queue discipline. It is controlled by thequeue vector q and the request vector r. When MAC’ is invokedby any system program (e.g., MAC’ in CPU line 3), then a requestfor service is entered (line 0) by setting ri to 1. If the queueis empty, the request is also entered in qi. In any case, the MAC’program dwells on line 1 until i is recognized as the “first” nonzeroentry in the queue. The queue discipline is not first-in firstout,but is in order by position in a permutation of q specifiedby the vector rank, which gives priority according to the index i,except that i = 0 (the multiplexor channel) may be assigned out oforder. This implies that the channels have priority over the intervaltimer which has priority over the CPU.Any request for service which is not entered dircctly in q online 0 is entered from r by line 24. If j3 # h, then q is respecifiedby Y (with ri already set to zero by line 2) except that a CPU requestis entered in qD only if w = 0. The variable w is controlled(line 2) only by MAC’, the timer update memory-access, and itremains at 0 or 1 according to whether the last use of MAC8 wasfor a store or for a fetch. This excludes the CPU from memoryduring the updating of the interval counter (TU lines 1, 3) andprevents the inadvertent overwriting (by TU line 3) of a newsetting of the interval timer counter by a CPU “store” instruction.However, the use of memory by 1/0 is not excluded by w.If j3 = h, line 24 leaves q unchanged and therefore preventsany other MAC from being executed until after the next use of thesame MAC with j, # h. The use of j, = h occurs only in theinstruction TS (test and set) as follows (EXC lines a29, 30)MACg(a,, 1, f, h; u)MAC’(a1, I, S, d; e (8)).Thus, the addressed byte is set immediately following a test ofits value, before any other access to memory can occur.208 A. D. FALKOFF. K. E. IVERSON. AND E. H. SUSSENGUTH