A formal description of SYSTEM/360

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example, 'J, in line 20 of MAC' (j; k), the memory access program.The system description comprises a set of tables and programs.Programs include system programs and defined operations. Allsystem programs operate concurrently and continuously, withprecisely one line active in each program at all times. This activeline will often be a dwell of the form shown in Figure 2. Theprogram breaks from the dwell only when the variable x is setto a nonzero value by some other program in the system.A defined operation is a program which operates only wheninvoked by some other program. It can be distinguished from asystem program by the presence of exit arrows. When called, adefined operation constitutes the active line of the program it isserving, and will itself have precisely one line active at a timeuntil an exit is reached.Variables occurring in the name of a defined operation (forexample, j and k in the case of MACi(j; k)) are dummy variableswhose values are determined by the values of the variables occurringin any particular use of the defined operation. Thus, theperformance of line d3 of EXC (that is, MAC' (aa, 2, f, d; a"/RU1))executes MAC' with j = (az, 2, f, d) and with k = al'/Ral.A study of MAC will show that this causes 2 bytes of data, fetchedfrom the memory location starting at a2, to be transferred to thelast sixteen positions of the general register whose index is a,.All components of the formal system are listed in Table 2.The text and figures, and the tables not listed, are intended forexposition only.Figure12 Dwellx:oTable 2CornDonents of formal descriotionSystem programsBMT Burst-mode timerCHc ChannelsCP Control panelCPU Central processing unitEIE External interruption entryEP Emergency pullES External signalspage2612612592592 592 592 59pageHFCc Hardware failure in channels 261ZOZE 1/0 interruption entry 261ZPL Initial program load 259MCZE Machine check interruption entry 259T Timer 259TOLE Time-out limiters 261TU Timer update 259Defined operationsPagepageDELAY* MODEL-DEPENDENT RESETDIAGNOSE* POWER-OFF SEQUENCE*EXC Instruction execution 240 POWER-ON SEQUENCEMAC'(j; k) Memory access 259 RESET 259MALFUNCTION RESET* SYSTEM STOP ** These operat,ions are not detailed in this description.Table 3 System reference table for programs and variables: symbol and dimension columns only 250Table 5 Navigation matrix Nand reference table: first 11 columns (navigation matrix) only 256Table 6 decoding Operation matrix 0: numericalonly entries258FORMAL DESCRIPTION OF SYSTEM/360 203
Table 4 Central processing unitprogram segmentsFunctionsCPUlinesInitial-program-load 0dwellInstruction fetch 1-7Instruction interpre- 8-10tationEffective address cal- 11-19culationInstruction execution 20-21Entry of program 22-24interruptionInterruption service 25-33Single-step, stop, and 34-36wait testsCPU programinstruction fetch(lines 1-7)instructioninterpretation(lines 8-10)204The central processing unitThe central processing system comprises the nine system programsshown on page 259, and the defined operations listed inTable 2. An overall view of the system can be gained from Table 3,which lists all variables occurring in the programs, indicates themeaning or significance of each symbol and the dimensions ofeach vector or matrix variable, and provides reference to everyprogram statement (or entire program) in which each variable isspecified or used. Since the range of each variable is readily deducedfrom its use in the programs, ranges are not explicitlyspecified in the table. Most of the variables are logical (i.e., havethe range 0, l), but some, such as the components of a, m, andN, are not. The ranges of the components of some arrays (e.g., N)are not all alike.Although Table 3 is designed for reference, it will also repaycareful initial study. It shows, for example, that the memory Mbehaves as a 9-bit wide memory of at most 224 8-bit bytes withparity, that each block of 2" bytes of M may be protected by a4-bit protection key K', and that 16 single-word general registersR and 4 double-word floating-point registers F are provided. Allof the more detailed information on the treatment of the variables(such as the formats used in instruction addresses) is immediatelyavailable in the programs.The core of the system is the CPU program, which describes thesequencing and execution of instructions and the servicing ofinterruptions. The functional segments of this program are listedin Table 4.An instruction may be 1, 2, or 3 half-words long and is fetchedby lines 3-7 (using the MAC operation detailed on page 259), twobytes at a time, from memory locations specified by the instructioncounter represented by ""/pa, the last 24 bits of the program statusword p. For each half-word fetched, the instruction length code(p32,) is augmented by 1 (line 4) and the instruction address by 2.The sum of the first 2 bits of the first half-word plus 1 determines(on line 7) the number of half-words fetched.Line 2 enters a specification exception if the protection featureis not installed (m, = 0) and any of positions 8-11 of p are nonzero.Addressing and specification exceptions are detected by lines 7-8of the MAC operation and are entered (MAC line 15) into tsand is, respectively. Either of these errors subsequently causes abranch from CPU line 6 to line 24, skipping the instruction executionphase and any remaining portion of the fetch.If the fetch concludes without error, lines 8-9 interpret theinstruction by selecting from the navigation matrix N (Table 5)a row N" to specify the vector n used in the subsequent controlof the instruction execution phase. The rowof N selected is determinedby the particular element of the operation decodingmatrix 0 (Table 6) selected by the 8-bit operation code in thefirst byte of the instruction. Table 6 displays the mnemonicsA. D. FALKOFF, K. E. IVERSON, AND E. H. SUSSENGUTH
Page 1: All SYSTEM/~~O functional character
Page 8 and 9: used for the instructions as well a
Page 10 and 11: this respecifies the instruction co
Page 12 and 13: ~The first 2’’ bytes of memory
Page 14 and 15: Indications of machine failure are
Page 16 and 17: TS (test and set) simply fetches on
Page 18 and 19: is suppressed (f12) by a protection
Page 20 and 21: in the case of ZAP (zero and add) a
Page 22 and 23: Input/outputThe SYSTEM/B~O input/ou
Page 24 and 25: one device and the initiation of a
Page 26 and 27: multiplexor channel it could be any
Page 28 and 29: code in C” (line 27). The pci bit
Page 30 and 31: channel operation as any other stat
Page 32 and 33: ~register os/s" (line 45), acknowle
Page 34 and 35: and Si = 1 is used to denote a pend
Page 36 and 37: In line 121 a multiplexor channel s
Page 38 and 39: mand chaining. Alternatively, the b
Page 40 and 41: Iithas no effect on a current opera
Page 42 and 43: for assistance in the early stages;
Page 44 and 45: EX "TM --DCT DCTR --BAL DALR --BCR
Page 48 and 49: MI'CrEDEDMK "EDMKEDEDYVN YVZTR MVCg
Page 50 and 51: AP CP DPMP BPZAPCVBCVBCPz;}BPMPDPAP
Page 52 and 53: k45k46k47k48k49k50k51k52k53k54k55k5
Page 54 and 55: Table 3 Continuedsymboldimensionsig
Page 56 and 57:
dimensionsignijicancereferences: se
Page 58 and 59:
Table 3Continuedsymboldimensionsign
Page 60 and 61:
~~~~~~~~~~I0 1 2 3 4 5 6 7 8 910 In
Page 62 and 63:
~~MCIE, machine check interruption
Page 64 and 65:
(=Ti, qi +- 1, -v/q 0-. -i : (qrand
Page 66:
C h d saivpa8:Ks;s;EMmpx ? 1 I&I ?
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A formal description of SYSTEM/360

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