A formal description of SYSTEM/360

instructions are suppressed by t2 (lines a1 and a25), both areprivileged and could, in a normal operating system, be executedonly in the supervisor program.What instructions are included in the floating-point feature?Table 3 shows that the feature options are specified by the machinecharacteristics vector m, and that m, identifies the floating-pointoption. The occurrences of m2 in column No of Table 5 thereforeidentify the floating-point instructions.Can data be transferred directly (i.e., not via memory)betweena general register Ri and a floating-point register F’?Comparing the ‘(Results” column of Table 5 with column Noshows that F is set only by floating-point instructions and Ris never set by floating-point instructions. Since R is set onlyby non-floating-point instructions and since Table 3 shows thatF is referred to only in floating-point instructions (segment kof EXC), direct transfer from F to R is impossible. Similarly,since F is set only by segment k of EXC, it remains only to scanthe argument fetch portion (k0-16) to see that R does not occur.Under what circumstances does the interval timer fail torecord elapsed time? The entry for timer alarm in Table 3 refersto the TU program whose dwell on line 0 contains the conditionsof interest. In particular, the last term prevents normal decrementationduring the dwell on line a17 of the read direct instruction.Moreover, normal decrementntion is delayed by the use of MAC8on TU line 1 if the channels (which have a higher priority) keepthe memory-access facility occupied.Can the console operator display the contents of the intervaltimer and tell if it is decreasing appropriately by watching thedisplay lights flicker? Line 18 of the CP program shows that anymemory location (in this case 80) selected by the address switchcan be displayed. However, this segment of the program (15-25)can, because of line 13, be reached only if the CPU is first stopped.Any displayed value is therefore fixed. In particular, the timer isnot updated when the CPU is stopped (TU line 0).How are program interruptions caused by shift instructions;what determines the amount of shift? Line el sets te (which thefootnote to Table 5 shows to be the “specificationexception”)for an odd first address in instructions SLDA, SRDA, SLDL, and SRDL.Line e9 sets t8 (fixed point overflow) for instructions SLA andSLDA if the mask fisc is on and a significant (differing from thesign) bit has been lost in the shift. The shifting is performed onlines e5, e6, e8 and e10, and the amount of shift is determinedon line e3 as the residue modulo 64 of the second effective address.What instructions employ three specifiable addresses? Table 3refers to EXC b18, 19, d17, 23 for effective address a,; the instructionsinvolved are therefore BXH, BXLE, LM, and STM.ACKNOWLEDGMENTWe are greatly indebted to many of our colleagues: to W. C. Carterof the Data Systems Division for suggesting the work; to C. H. Liu238 A. D. FALKOFF, K. E. IVERSON, AND E. H. SUSSENGUTH