A formal description of SYSTEM/360

of the EXC operation appropriate to the particular instructionbeing executed. For example, if the instruction is LR, then n3is specified by N,?', and n3 = do. This is also indicated informallyby the "LR" written to the left of line do.To continue the example, line do specifies the value of generalregister R"' by the value of Ras, and the exit arrow on the sameline indicates that EXC is complete.The execute instruction (EX) beginning on line bo, furnishes asomewhat more complex example of the execution phase. Exceptthat the length code p32,33 and the instruction counter arenot disturbed, lines bo-3 are like the instruction fetch (CPU 3-7)and therefore load the instruction register with the data beginningat byte address a2 in memory. Since n3 = bo in this case, line 21of CPU subsequently causes (unless a program interruption hasbeen entered in t, either on line b5 or by use of MAC on line bl)a branch to line 8, thus interpreting and executing the instructionjust fetched by the EX instruction, without disturbing the instructioncounter. If this subject instruction is itself an EX, it hasthe operation code 0100 0100, and line b5 therefore enters anexecute exception and line 21 does not cause a branch, thusaborting the execution of the subject EX instruction. The phrasel5 A l6 in line b5 prevents a spurious execute exception if addressingor specification exceptions have already occurred.If the first operand address of EX is nonzero, then line b4 willor the last byte of general register P with the last byte of thefirst half-word of the subject instruction. This permits a programmerto specify such parameters as length, index, or immediatedata in the subject instruction indirectly via R"'.If no program interruption has been generated by the precedingentry of program fetch and execution, each component of t will be zero, and linesinterruption 23 and 24 will be skipped. Otherwise line 24 presents the inter-(lines 22-24) ruption by setting h, to 1 and entering an appropriate code inpositions 16-31 of p. Thus, if the interruption is occasioned by aninterruptionservice(lines 25-33)addressing exception, ta = 1, the expression t/ 1" yields 5, andits base 2 representation (namely, 0000 0000 0000 0101) isentered in p. If multiple causes of program interruption occur,then one of the appropriate codes will be selected at random andstored in p. For example, if tg = te = 1, then t/ r" = (5, 6) and?'/(5, 6) selects one of 5 and 6.If the cause of the program interruption entry is neither t4nor t5 (that is, neither a protection nor an addressing exception),then the instruction length code p32,33 is unchanged by line 23;otherwise line 23 may set the length code to zero.Other types of interruptions are entered in other componentsof h by other programs (listed in the reference column of Table 3)whose details will be considered later.An interruption service places an appropriate code in bits16-31 of p, stores p in memory at one of five fixed locations deter-mined by the type of interruption (line 31), and finally respecifiesp (line 32) from one of five other fixed memory locations. Since206 A. D. FALKOFF, K. E. IVERSON, AND E. H. SUSSENGUTH