A formal description of SYSTEM/360

used for the instructions as well as the index to N, which is theonly formal part of the matrix 0. Similarly, Table 5 includesmuch informal information in addition to the formal specificationof the matrix N.Except for its first twocomponents, the navigation vector nis of formal interest only, since the sequences it determines inthe CPU program (line 11) and in the EXC operation are alsoindicated informally by broken-line arrows and labels. If the8-bit operation code corresponds to no installed operation, thenno = 0 and an operation exception exists (line lo); if the operationis privileged (n, = 1) and if fils = 1 (that is, the processor isin the problem stale as opposed to the supervisor state), a privilegedoperation exception exists.The manner of specifying the operands of an instruction is afunction of the format of that instruction. Most instructions specifytwo operands; the efective addresses of the first and second operandsare computed as a, and a,, respectively. Normally, the addressesare used to select two generalregisters (RR format), a registerand storage in memory (RS), a register and storage with a secondregister for indexing (RX), two areas in storage (SS) or storageand immediate data from the instruction itself (SI), all as indicatedin Table 7. However, since many exceptions exist, Table 7 shouldbe considered as a guide only, all operands being explicitly definedin EXC. Some instructions in the RS format use a thirdaddress a8. A terminal R and a terminal I in instruction mnemonicsusually indicate the RR and SI formats, respectively.For instructions in the SS format, the lengths of the operandsare defined by line 17; I , + 1 and I , + 1 are the lengths (in bytes)of the first and second operands, and Io + 1 is the length for someinstructions in which a single length is required. Again, the matrixN (and hence n) provides (via CPU line 11) the formal specificationof the format used by each instruction.The calculation of the effective addresses is straightforwardand will be discussed only for the RX and RS cases. In the lattercase, the second operand address a2 is determined by the secondhalf-word of the instruction and is formed by adding to the valueof its last 12 bits ( Lml'/Z1) the value of the general register selectedby its first 4 bits (I RLU*'"), unless the zeroth register is selected(0 = La4/Z1), in which case zero is added. Finally, the residue ofthis sum modulo zz4 specifies a,. The first and third operand addressesare determined by the values of groups of 4 bits in the firsthalf-word, La4/m4/Zo and lw4/Z0, respectively. The RX formatdiffers only in that the index quantity contained in the generalregister selected by the last 4 bits of the first half-wordis (again, unless the zeroth register is selected) also added to thesum used to determine a,, and in that the third address is notapplicable.The calculation of the effective address is immediately followedby a use of the defined operation EXC on line 20. This operationbegins with a branch from line 0 to line n3, that is, to the segmenteffective addresscalculation(lines 11-19)instructionexecution(lines 20-21)FORMAL DESCRIPTIONOF SPSTEM/360205