A formal description of SYSTEM/360

TS (test and set) simply fetches one byte u from memory(a29), sets the condition code to (0, u,,), and sets the same bytein memory to all 1’s. The significant characteristic of this instructionis that (because of the “hold” h in the first use of MAC)it sets the tested byte in memory before any other reference tomemory can occur.EX (execute) mas discussed in conjunction with the C’PUprogram. TM (test under mask) sets the condition code as shownon line b7. Thus, the code is (0, 0) if the immediate data byte(as//) is entirely zero; otherwise, the first bit is set to 1 if allbits of (o*//)/u are 1, whereas the second bit is set if any bitof (as/ P) /u is 1. The expression (as//)/u denotes the componentsof the byte u from memory which are extracted by the nonzerobits of the immediate data byte.The branch instructions set the instruction counter conditionallyas shown, and can therefore be used to alter the normalsequence of instruction execution. A full appreciation of BXH(branch on index high) and BXLE depends upon a knowledgeof the 2’s conlplement representation of signed numbers, whichis also used in the fixed-point arithmetic instructions.A logical vector (register) u of dimension d represents anyinteger n in the range - F 1 to 2“” - I in the for111n = (I u) - u,, x 2”.For example, if d = 3 the representation scheme is given inTable 8.It is easily verified that the representation of a number nin the appropriate range is given by the statementu +- /(d)Tn;(n < 0); -(d)T In + l/.Arithnlctic operations (such as the sunmation occurring in BXH(line b20)) may, however, produce a result outside the representablerange. The representation shown above is, however, usedeven in this case. The matter is illustrated in Table 9 by examplescomputed for a dimension d = 4.For the BXH instruction, lines b17-1!) show the specificationof k,, k,, and k, as the signed numbers represented in generalregisters ul, a3, and either ua + I (if uR is even) or us (if us is odd).Register u1 is then respecified by the 2’s complement representationof the sum k,, + k,. The value of this result is compared withk, (line b23) to dcterminc whether to lmnch to a2.The four 1/0 instructions are all privileged (line cO), determinea channel address from the first threc of the last eleven bits ofthe first operand address, test whether the indicated channel isoperational (line c2), and conclude by setting the condition codeto (1, 1) if it is not. If the channel selected is the lnultiplexor channel(i = 0) and a “burst nlodc” timer has not run out, then cfjdwells for a maximum of about 100 microseconds before testing(line c6) whether the channel is busy.If the channel is busy, the condition code is set to(1, 0) onFORMAL DESCRIPTION OF SYSTEM/36Obranches, execute,test under mask(lines bo-24)Table 8Table 9nU~3 0112 0101 0010 000-1 111-2 110-3 101-4 100ltepre- Intersenta-preta-‘n tion tion______Pfl 1001 -623 1000 -723-1 0111 $7-23 1000 -8-(23+1) 0111 +7-(Z3+2) 0110 +6input/output(lines c0-15)213