A formal description of SYSTEM/360

loads the condition code in p, and signals the CPU by settinggo to zero.A busy multiplexor channel with non-matching addresses mustcheck the subchannel storage location indicated by the interruptionaddress and, if the interruption is for a pci or termination(line 15), generate a CSW and clear the subchannel (lines 18 and19) much like CH lines 136 and 137. If the subchannel test (line 16)results in the branch to line 17, the bit 9, is set to 1 and the programreturns to line 0 as in the other cases. I-Towever, the CPU willrecognize g1 (line 30) as an indication that information for theproffered interruption was not available and it will not executethe usual interruption procedure.BMT is a time-limiting clock with two ways of stopping. Itburst mode timer is started by setting g2 in CHo, line 48 or 165, and it runs untiland time-out stopped by B: = 0 (line 5) or by its counter running out (line 4).limiter Where performance requirements permit, channels make useof CPU facilities and controls to varying degrees. The effect oft'his on the logical behavior of the channels is confined to therecognition of hardware failures and consequent corrective action.Program TOE is relevant where CPU controls are preempted forchannel interface operations, so that an independent means forpreventing indefinite delays is required. Two such levels are distinguishedin TOL". If CWa = 1, channel c uses CPU controlsfor all interface operations other than polling in the channelidle phase, and if Cw = 1, it uses these controls for polling aswell. Thus if CWa = 1, the dwell on line 1 is broken each time& = 1 and either CW8 = 1 or one of the interface tag lines isnonzero. (The polling during channel idle is distinguished from allother interface operations by Vi = 1 and (///a3/ UC) = 0.)In TOL" there are two time-limiting clocks in series. The firstclock, which is started in line 2, times either the establishment ofa connection (q = l), or the return of select-in (PwG = l), orany response at all ( = 0). The maximum time for the dwellencompassing lines 3-5 is of the order of 32 microseconds. When aconnection is established (G = 1) (possibly, in the case of datatransfer, even before the first clock is started), the maximumtime is of the order of 500 milliseconds. This clock is stoppcd eitherby Q = 0, indicating a response of some kind from the device,or by = 0, indicating that the device wishes to disconnect.If either clock runs out before it is stopped, an interface controlcheck is set in linc 0 and detected in CH" in one of lines 63, 117,or 126, or in HFC line 1.Program HFC" distinguishes between the case where the chan-hardware nel shares both data paths and controls with the CPU (Cw = 1)failure inchannelon the one hand, and all other degrees of sharing and independenceon the other. Thus, in line 1, the dwell is broken in all cases for achannel control cl~eclc"' (Si), but, is not disturbed for either a channeldata check (Si) or interface control check (Si) unless CM; = 1.Whereas an interface control check will be acted upon by programCH" in any case, a channel data check will not, and hence236 A. D. FALKOFF, K. E. IVERSON, AND E. H. SUSSENGUTH