Xilinx Virtex-6 Libraries Guide for HDL Designs

Virtex-6 Libraries Guide forHDL DesignsUG623 (v 11.4) December 2, 2009

Xilinx Trademarks and Copyright InformationXilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to yousolely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce,distribute, republish, download, display, post, or transmit the Documentation in any form or by any meansincluding, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the priorwritten consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation.Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinxassumes no obligation to correct any errors contained in the Documentation, or to advise you of any correctionsor updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may beprovided to you in connection with the Information.THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINXMAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDINGTHE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR APARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILLXILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTALDAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THEDOCUMENTATION.© Copyright 2002-2009 Xilinx Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and otherdesignated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property oftheir respective owners.Virtex-6 Libraries Guide for HDL Designs2 www.xilinx.com UG623 (v 11.4) December 2, 2009

Table of ContentsXilinx Trademarks and Copyright Information......................................................................................... 2Chapter 1 About this Guide......................................................................................................................... 15Design Entry Methods.......................................................................................................................... 15Chapter 2 About Unimacros........................................................................................................................ 17BRAM_SDP_MACRO .......................................................................................................................... 18Introduction.................................................................................................................................. 18Port Description ............................................................................................................................ 18Configuration Table....................................................................................................................... 19Design Entry Method .................................................................................................................... 19Available Attributes ...................................................................................................................... 19For More Information.................................................................................................................... 26BRAM_SINGLE_MACRO .................................................................................................................... 27Introduction.................................................................................................................................. 27Port Description ............................................................................................................................ 27Configuration Table....................................................................................................................... 28Design Entry Method .................................................................................................................... 30Available Attributes ...................................................................................................................... 30For More Information.................................................................................................................... 35BRAM_TDP_MACRO.......................................................................................................................... 36Introduction.................................................................................................................................. 36Port Description ............................................................................................................................ 36Configuration Table....................................................................................................................... 37Design Entry Method .................................................................................................................... 39Available Attributes ...................................................................................................................... 39For More Information.................................................................................................................... 45FIFO_DUALCLOCK_MACRO ............................................................................................................. 46Introduction.................................................................................................................................. 46Port Description ............................................................................................................................ 46Configuration Table....................................................................................................................... 47Design Entry Method .................................................................................................................... 47Available Attributes ...................................................................................................................... 48For More Information.................................................................................................................... 49FIFO_SYNC_MACRO .......................................................................................................................... 50Introduction.................................................................................................................................. 50Port Description ............................................................................................................................ 50Configuration Table....................................................................................................................... 51Design Entry Method .................................................................................................................... 51Available Attributes ...................................................................................................................... 52For More Information.................................................................................................................... 53ADDMACC_MACRO .......................................................................................................................... 54Introduction.................................................................................................................................. 54Port Description ............................................................................................................................ 54Design Entry Method .................................................................................................................... 55Available Attributes ...................................................................................................................... 55For More Information.................................................................................................................... 56ADDSUB_MACRO .............................................................................................................................. 57Introduction.................................................................................................................................. 57Port Description ............................................................................................................................ 57Design Entry Method .................................................................................................................... 57Available Attributes ...................................................................................................................... 58For More Information.................................................................................................................... 59COUNTER_LOAD_MACRO ................................................................................................................ 60Introduction.................................................................................................................................. 60Port Description ............................................................................................................................ 60Design Entry Method .................................................................................................................... 60Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 3

Available Attributes ...................................................................................................................... 61For More Information.................................................................................................................... 62COUNTER_TC_MACRO ..................................................................................................................... 63Introduction.................................................................................................................................. 63Port Description ............................................................................................................................ 63Design Entry Method .................................................................................................................... 63Available Attributes ...................................................................................................................... 64For More Information.................................................................................................................... 65EQ_COMPARE_MACRO ..................................................................................................................... 66Introduction.................................................................................................................................. 66Port Description ............................................................................................................................ 66Design Entry Method .................................................................................................................... 66Available Attributes ...................................................................................................................... 67For More Information.................................................................................................................... 68MACC_MACRO.................................................................................................................................. 69Introduction.................................................................................................................................. 69Port Description ............................................................................................................................ 69Design Entry Method .................................................................................................................... 70Available Attributes ...................................................................................................................... 70For More Information.................................................................................................................... 71DSP_MULT_MACRO........................................................................................................................... 72Introduction.................................................................................................................................. 72Port Description ............................................................................................................................ 72Design Entry Method .................................................................................................................... 72Available Attributes ...................................................................................................................... 73For More Information.................................................................................................................... 74Chapter 3 Functional Categories .................................................................................................................. 75Chapter 4 About Design Elements ............................................................................................................... 81AND2B1L ........................................................................................................................................... 82Introduction.................................................................................................................................. 82Logic Table ................................................................................................................................... 82Port Descriptions........................................................................................................................... 82Design Entry Method .................................................................................................................... 82For More Information.................................................................................................................... 82BSCAN_VIRTEX6 ................................................................................................................................ 83Introduction.................................................................................................................................. 83Port Descriptions........................................................................................................................... 84Design Entry Method .................................................................................................................... 84Available Attributes ...................................................................................................................... 84For More Information.................................................................................................................... 85BUFG.................................................................................................................................................. 86Introduction.................................................................................................................................. 86Port Descriptions........................................................................................................................... 86Design Entry Method .................................................................................................................... 86For More Information.................................................................................................................... 87BUFGCE ............................................................................................................................................. 88Introduction.................................................................................................................................. 88Logic Table ................................................................................................................................... 88Design Entry Method .................................................................................................................... 88For More Information.................................................................................................................... 89BUFGCE_1 .......................................................................................................................................... 90Introduction.................................................................................................................................. 90Logic Table ................................................................................................................................... 90Design Entry Method .................................................................................................................... 90For More Information.................................................................................................................... 91BUFGCTRL ......................................................................................................................................... 92Introduction.................................................................................................................................. 92Port Descriptions........................................................................................................................... 92Design Entry Method .................................................................................................................... 92Virtex-6 Libraries Guide for HDL Designs4 www.xilinx.com UG623 (v 11.4) December 2, 2009

Available Attributes ...................................................................................................................... 93For More Information.................................................................................................................... 93BUFGMUX.......................................................................................................................................... 94Introduction.................................................................................................................................. 94Logic Table ................................................................................................................................... 94Port Descriptions........................................................................................................................... 94Design Entry Method .................................................................................................................... 94Available Attributes ...................................................................................................................... 95For More Information.................................................................................................................... 95BUFGMUX_1....................................................................................................................................... 96Introduction.................................................................................................................................. 96Logic Table ................................................................................................................................... 96Design Entry Method .................................................................................................................... 96For More Information.................................................................................................................... 97BUFGMUX_CTRL................................................................................................................................ 98Introduction.................................................................................................................................. 98Port Descriptions........................................................................................................................... 98Design Entry Method .................................................................................................................... 98For More Information.................................................................................................................... 99BUFGP...............................................................................................................................................100Introduction.................................................................................................................................100Design Entry Method ...................................................................................................................100For More Information...................................................................................................................100BUFH.................................................................................................................................................101Introduction.................................................................................................................................101Port Descriptions..........................................................................................................................101Design Entry Method ...................................................................................................................101For More Information...................................................................................................................101BUFHCE ............................................................................................................................................102Introduction.................................................................................................................................102Port Descriptions..........................................................................................................................102Design Entry Method ...................................................................................................................102Available Attributes .....................................................................................................................102For More Information...................................................................................................................103BUFIO................................................................................................................................................104Introduction.................................................................................................................................104Port Descriptions..........................................................................................................................104Design Entry Method ...................................................................................................................104For More Information...................................................................................................................105BUFIODQS.........................................................................................................................................106Introduction.................................................................................................................................106Port Descriptions..........................................................................................................................106Design Entry Method ...................................................................................................................106Available Attributes .....................................................................................................................106For More Information...................................................................................................................107BUFR .................................................................................................................................................108Introduction.................................................................................................................................108Port Descriptions..........................................................................................................................108Design Entry Method ...................................................................................................................108Available Attributes .....................................................................................................................108For More Information...................................................................................................................109CAPTURE_VIRTEX6...........................................................................................................................110Introduction.................................................................................................................................110Port Descriptions..........................................................................................................................110Design Entry Method ...................................................................................................................110Available Attributes .....................................................................................................................110For More Information...................................................................................................................111CARRY4.............................................................................................................................................112Introduction.................................................................................................................................112Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 5

Port Descriptions..........................................................................................................................112Design Entry Method ...................................................................................................................112For More Information...................................................................................................................113CFGLUT5...........................................................................................................................................114Introduction.................................................................................................................................114Port Descriptions..........................................................................................................................114Design Entry Method ...................................................................................................................115Available Attributes .....................................................................................................................115For More Information...................................................................................................................116DCIRESET..........................................................................................................................................117Introduction.................................................................................................................................117Port Descriptions..........................................................................................................................117Design Entry Method ...................................................................................................................117Available Attributes .....................................................................................................................117For More Information...................................................................................................................118DNA_PORT .......................................................................................................................................119Introduction.................................................................................................................................119Port Descriptions..........................................................................................................................119Design Entry Method ...................................................................................................................119Available Attributes .....................................................................................................................120For More Information...................................................................................................................120DSP48E1 ............................................................................................................................................121Introduction.................................................................................................................................121Port Descriptions..........................................................................................................................122Design Entry Method ...................................................................................................................124Available Attributes .....................................................................................................................124For More Information...................................................................................................................129EFUSE_USR .......................................................................................................................................130Introduction.................................................................................................................................130Port Descriptions..........................................................................................................................130Design Entry Method ...................................................................................................................130Available Attributes .....................................................................................................................130For More Information...................................................................................................................131FDCE .................................................................................................................................................132Introduction.................................................................................................................................132Logic Table ..................................................................................................................................132Design Entry Method ...................................................................................................................132Available Attributes .....................................................................................................................132For More Information...................................................................................................................133FDPE .................................................................................................................................................134Introduction.................................................................................................................................134Logic Table ..................................................................................................................................134Design Entry Method ...................................................................................................................134Available Attributes .....................................................................................................................134For More Information...................................................................................................................134FDRE .................................................................................................................................................135Introduction.................................................................................................................................135Logic Table ..................................................................................................................................135Design Entry Method ...................................................................................................................135Available Attributes .....................................................................................................................135For More Information...................................................................................................................135FDSE..................................................................................................................................................136Introduction.................................................................................................................................136Logic Table ..................................................................................................................................136Design Entry Method ...................................................................................................................136Available Attributes .....................................................................................................................136For More Information...................................................................................................................136FIFO18E1 ...........................................................................................................................................137Introduction.................................................................................................................................137Virtex-6 Libraries Guide for HDL Designs6 www.xilinx.com UG623 (v 11.4) December 2, 2009

Port Descriptions..........................................................................................................................137Design Entry Method ...................................................................................................................138Available Attributes .....................................................................................................................138For More Information...................................................................................................................140FIFO36E1 ...........................................................................................................................................141Introduction.................................................................................................................................141Port Descriptions..........................................................................................................................141Design Entry Method ...................................................................................................................142Available Attributes .....................................................................................................................142For More Information...................................................................................................................144FRAME_ECC_VIRTEX6 ......................................................................................................................145Introduction.................................................................................................................................145Port Descriptions..........................................................................................................................145Design Entry Method ...................................................................................................................146Available Attributes .....................................................................................................................146For More Information...................................................................................................................147GTHE1_QUAD...................................................................................................................................148Introduction.................................................................................................................................149Design Entry Method ...................................................................................................................149For More Information...................................................................................................................149GTXE1 ...............................................................................................................................................150Introduction.................................................................................................................................150Design Entry Method ...................................................................................................................151For More Information...................................................................................................................151IBUF ..................................................................................................................................................152Introduction.................................................................................................................................152Port Descriptions..........................................................................................................................152Design Entry Method ...................................................................................................................152Available Attributes .....................................................................................................................152For More Information...................................................................................................................153IBUFDS..............................................................................................................................................154Introduction.................................................................................................................................154Logic Table ..................................................................................................................................154Port Descriptions..........................................................................................................................154Design Entry Method ...................................................................................................................154Available Attributes .....................................................................................................................154For More Information...................................................................................................................155IBUFDS_GTHE1 .................................................................................................................................156Introduction.................................................................................................................................156Design Entry Method ...................................................................................................................156For More Information...................................................................................................................156IBUFDS_GTXE1..................................................................................................................................157Introduction.................................................................................................................................157Design Entry Method ...................................................................................................................157For More Information...................................................................................................................157IBUFG................................................................................................................................................158Introduction.................................................................................................................................158Port Descriptions..........................................................................................................................158Design Entry Method ...................................................................................................................158Available Attributes .....................................................................................................................158For More Information...................................................................................................................159IBUFGDS ...........................................................................................................................................160Introduction.................................................................................................................................160Logic Table ..................................................................................................................................160Port Descriptions..........................................................................................................................160Design Entry Method ...................................................................................................................160Available Attributes .....................................................................................................................161For More Information...................................................................................................................161ICAP_VIRTEX6 ..................................................................................................................................162Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 7

Introduction.................................................................................................................................162Port Descriptions..........................................................................................................................162Design Entry Method ...................................................................................................................162Available Attributes .....................................................................................................................162For More Information...................................................................................................................163IDDR .................................................................................................................................................164Introduction.................................................................................................................................164Port Descriptions..........................................................................................................................164Design Entry Method ...................................................................................................................165Available Attributes .....................................................................................................................165For More Information...................................................................................................................166IDDR_2CLK .......................................................................................................................................167Introduction.................................................................................................................................167Port Descriptions..........................................................................................................................167Design Entry Method ...................................................................................................................168Available Attributes .....................................................................................................................168For More Information...................................................................................................................169IOBUF................................................................................................................................................170Introduction.................................................................................................................................170Logic Table ..................................................................................................................................170Port Descriptions..........................................................................................................................170Design Entry Method ...................................................................................................................170Available Attributes .....................................................................................................................171For More Information...................................................................................................................172IOBUFDS ...........................................................................................................................................173Introduction.................................................................................................................................173Logic Table ..................................................................................................................................173Port Descriptions..........................................................................................................................173Design Entry Method ...................................................................................................................173Available Attributes .....................................................................................................................173For More Information...................................................................................................................174IODELAYE1 .......................................................................................................................................175Introduction.................................................................................................................................175Port Descriptions..........................................................................................................................175Design Entry Method ...................................................................................................................176Available Attributes .....................................................................................................................176For More Information...................................................................................................................178ISERDESE1.........................................................................................................................................179Introduction.................................................................................................................................179Port Descriptions..........................................................................................................................179Design Entry Method ...................................................................................................................180Available Attributes .....................................................................................................................180For More Information...................................................................................................................184KEEPER .............................................................................................................................................185Introduction.................................................................................................................................185Port Descriptions..........................................................................................................................185Design Entry Method ...................................................................................................................185For More Information...................................................................................................................186LDCE.................................................................................................................................................187Introduction.................................................................................................................................187Logic Table ..................................................................................................................................187Design Entry Method ...................................................................................................................187Available Attributes .....................................................................................................................187For More Information...................................................................................................................187LDPE .................................................................................................................................................188Introduction.................................................................................................................................188Logic Table ..................................................................................................................................188Design Entry Method ...................................................................................................................188Available Attributes .....................................................................................................................188Virtex-6 Libraries Guide for HDL Designs8 www.xilinx.com UG623 (v 11.4) December 2, 2009

For More Information...................................................................................................................188LUT5 .................................................................................................................................................189Introduction.................................................................................................................................189Logic Table ..................................................................................................................................190Port Description ...........................................................................................................................191Design Entry Method ...................................................................................................................191Available Attributes .....................................................................................................................191For More Information...................................................................................................................192LUT5_D .............................................................................................................................................193Introduction.................................................................................................................................193Logic Table ..................................................................................................................................194Port Description ...........................................................................................................................195Design Entry Method ...................................................................................................................195Available Attributes .....................................................................................................................195For More Information...................................................................................................................196LUT5_L..............................................................................................................................................197Introduction.................................................................................................................................197Logic Table ..................................................................................................................................198Port Description ...........................................................................................................................199Design Entry Method ...................................................................................................................199Available Attributes .....................................................................................................................199For More Information...................................................................................................................200LUT6 .................................................................................................................................................201Introduction.................................................................................................................................201Logic Table ..................................................................................................................................201Port Description ...........................................................................................................................203Design Entry Method ...................................................................................................................203Available Attributes .....................................................................................................................204For More Information...................................................................................................................204LUT6_2 ..............................................................................................................................................205Introduction.................................................................................................................................205Logic Table ..................................................................................................................................205Port Descriptions..........................................................................................................................207Design Entry Method ...................................................................................................................207Available Attributes .....................................................................................................................207For More Information...................................................................................................................208LUT6_D .............................................................................................................................................209Introduction.................................................................................................................................209Logic Table ..................................................................................................................................209Port Description ...........................................................................................................................211Design Entry Method ...................................................................................................................211Available Attributes .....................................................................................................................212For More Information...................................................................................................................212LUT6_L..............................................................................................................................................213Introduction.................................................................................................................................213Logic Table ..................................................................................................................................213Port Description ...........................................................................................................................215Design Entry Method ...................................................................................................................215Available Attributes .....................................................................................................................216For More Information...................................................................................................................216MMCM_ADV.....................................................................................................................................217Introduction.................................................................................................................................217Port Descriptions..........................................................................................................................217Design Entry Method ...................................................................................................................219Available Attributes .....................................................................................................................219For More Information...................................................................................................................223MMCM_BASE ....................................................................................................................................224Introduction.................................................................................................................................224Port Descriptions..........................................................................................................................224Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 9

Design Entry Method ...................................................................................................................225Available Attributes .....................................................................................................................225For More Information...................................................................................................................228MUXF7 ..............................................................................................................................................229Introduction.................................................................................................................................229Logic Table ..................................................................................................................................229Port Descriptions..........................................................................................................................229Design Entry Method ...................................................................................................................229For More Information...................................................................................................................230MUXF7_D ..........................................................................................................................................231Introduction.................................................................................................................................231Logic Table ..................................................................................................................................231Port Descriptions..........................................................................................................................231Design Entry Method ...................................................................................................................231For More Information...................................................................................................................232MUXF7_L...........................................................................................................................................233Introduction.................................................................................................................................233Logic Table ..................................................................................................................................233Port Descriptions..........................................................................................................................233Design Entry Method ...................................................................................................................233For More Information...................................................................................................................234MUXF8 ..............................................................................................................................................235Introduction.................................................................................................................................235Logic Table ..................................................................................................................................235Port Descriptions..........................................................................................................................235Design Entry Method ...................................................................................................................235For More Information...................................................................................................................236MUXF8_D ..........................................................................................................................................237Introduction.................................................................................................................................237Logic Table ..................................................................................................................................237Port Descriptions..........................................................................................................................237Design Entry Method ...................................................................................................................237For More Information...................................................................................................................238MUXF8_L...........................................................................................................................................239Introduction.................................................................................................................................239Logic Table ..................................................................................................................................239Port Descriptions..........................................................................................................................239Design Entry Method ...................................................................................................................239For More Information...................................................................................................................240OBUF.................................................................................................................................................241Introduction.................................................................................................................................241Port Descriptions..........................................................................................................................241Design Entry Method ...................................................................................................................241Available Attributes .....................................................................................................................241For More Information...................................................................................................................242OBUFDS ............................................................................................................................................243Introduction.................................................................................................................................243Logic Table ..................................................................................................................................243Port Descriptions..........................................................................................................................243Design Entry Method ...................................................................................................................243Available Attributes .....................................................................................................................243For More Information...................................................................................................................244OBUFTDS ..........................................................................................................................................245Introduction.................................................................................................................................245Logic Table ..................................................................................................................................245Port Descriptions..........................................................................................................................245Design Entry Method ...................................................................................................................245Available Attributes .....................................................................................................................245For More Information...................................................................................................................246Virtex-6 Libraries Guide for HDL Designs10 www.xilinx.com UG623 (v 11.4) December 2, 2009

ODDR................................................................................................................................................247Introduction.................................................................................................................................247Port Descriptions..........................................................................................................................247Design Entry Method ...................................................................................................................247Available Attributes .....................................................................................................................248For More Information...................................................................................................................248OR2L .................................................................................................................................................249Introduction.................................................................................................................................249Logic Table ..................................................................................................................................249Port Descriptions..........................................................................................................................249Design Entry Method ...................................................................................................................249For More Information...................................................................................................................249OSERDESE1 .......................................................................................................................................250Introduction.................................................................................................................................250Port Descriptions..........................................................................................................................250Design Entry Method ...................................................................................................................252Available Attributes .....................................................................................................................252For More Information...................................................................................................................254PCIE_2_0............................................................................................................................................255Introduction.................................................................................................................................256Design Entry Method ...................................................................................................................256For More Information...................................................................................................................256PULLDOWN......................................................................................................................................257Introduction.................................................................................................................................257Port Descriptions..........................................................................................................................257Design Entry Method ...................................................................................................................257For More Information...................................................................................................................258PULLUP.............................................................................................................................................259Introduction.................................................................................................................................259Port Descriptions..........................................................................................................................259Design Entry Method ...................................................................................................................259For More Information...................................................................................................................260RAM128X1D ......................................................................................................................................261Introduction.................................................................................................................................261Port Descriptions..........................................................................................................................261Design Entry Method ...................................................................................................................262Available Attributes .....................................................................................................................262For More Information...................................................................................................................262RAM256X1S .......................................................................................................................................263Introduction.................................................................................................................................263Port Descriptions..........................................................................................................................263Design Entry Method ...................................................................................................................263Available Attributes .....................................................................................................................264For More Information...................................................................................................................264RAM32M ...........................................................................................................................................265Introduction.................................................................................................................................265Port Descriptions..........................................................................................................................266Design Entry Method ...................................................................................................................266Available Attributes .....................................................................................................................267For More Information...................................................................................................................268RAM32X1S.........................................................................................................................................269Introduction.................................................................................................................................269Logic Table ..................................................................................................................................269Design Entry Method ...................................................................................................................269Available Attributes .....................................................................................................................269For More Information...................................................................................................................270RAM64M ...........................................................................................................................................271Introduction.................................................................................................................................271Port Descriptions..........................................................................................................................272Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 11

Design Entry Method ...................................................................................................................272Available Attributes .....................................................................................................................273For More Information...................................................................................................................274RAM64X1D ........................................................................................................................................275Introduction.................................................................................................................................275Logic Table ..................................................................................................................................275Design Entry Method ...................................................................................................................276Available Attributes .....................................................................................................................276For More Information...................................................................................................................277RAM64X1S.........................................................................................................................................278Introduction.................................................................................................................................278Logic Table ..................................................................................................................................278Design Entry Method ...................................................................................................................278Available Attributes .....................................................................................................................278For More Information...................................................................................................................279RAMB18E1.........................................................................................................................................280Introduction.................................................................................................................................280Port Descriptions..........................................................................................................................280Design Entry Method ...................................................................................................................282Available Attributes .....................................................................................................................282For More Information...................................................................................................................288RAMB36E1.........................................................................................................................................289Introduction.................................................................................................................................289Port Descriptions..........................................................................................................................290Design Entry Method ...................................................................................................................291Available Attributes .....................................................................................................................291For More Information...................................................................................................................301SRL16E ..............................................................................................................................................302Introduction.................................................................................................................................302Logic Table ..................................................................................................................................302Port Descriptions..........................................................................................................................303Design Entry Method ...................................................................................................................303Available Attributes .....................................................................................................................303For More Information...................................................................................................................304SRLC32E ............................................................................................................................................305Introduction.................................................................................................................................305Port Descriptions..........................................................................................................................305Design Entry Method ...................................................................................................................306Available Attributes .....................................................................................................................306For More Information...................................................................................................................307STARTUP_VIRTEX6 ...........................................................................................................................308Introduction.................................................................................................................................308Port Descriptions..........................................................................................................................309Design Entry Method ...................................................................................................................309Available Attributes .....................................................................................................................309For More Information...................................................................................................................311SYSMON............................................................................................................................................312Introduction.................................................................................................................................312Port Descriptions..........................................................................................................................312Design Entry Method ...................................................................................................................313Available Attributes .....................................................................................................................313For More Information...................................................................................................................316TEMAC_SINGLE................................................................................................................................317Introduction.................................................................................................................................317Design Entry Method ...................................................................................................................318For More Information...................................................................................................................318USR_ACCESS_VIRTEX6 .....................................................................................................................319Introduction.................................................................................................................................319Port Descriptions..........................................................................................................................319Virtex-6 Libraries Guide for HDL Designs12 www.xilinx.com UG623 (v 11.4) December 2, 2009

Design Entry Method ...................................................................................................................319For More Information...................................................................................................................320Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 13

Virtex-6 Libraries Guide for HDL Designs14 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 1About this GuideThis HDL guide is part of the ISE documentation collection. A separate version of this guide is available if youprefer to work with schematics.This guide contains the following:• Introduction.• A list of design elements supported in this architecture, organized by functional categories.• Individual descriptions of each available primitive.Design Entry MethodsFor each design element in this guide, Xilinx evaluates the four options and recommends what we believe is thebest solution for you. The four options are:• Instantiation - This component can be instantiated directly into the design. This method is useful if you wantto control the exact placement of the individual blocks.• Inference - This component can be inferred by most supported synthesis tools. You should use this method ifyou want to have complete flexibility and portability of the code to multiple architectures. Inference also givesthe tools the ability to optimize for performance, area, or power, as specified by the user to the synthesis tool.• Coregen & Wizards - This component can be used through Coregen or Wizards. You should use this methodif you want to build large blocks of any FPGA primitive that cannot be inferred. When using this flow, youwill have to re-generate your cores for each architecture that you are targeting.• Macro Support - This component has a UniMacro that can be used. These components are in the UniMacrolibrary in the Xilinx tool, and are used to instantiate primitives that are complex to instantiate by just usingthe primitives. The synthesis tools will automatically expand the unimacros to their underlying primitives.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 15

Virtex-6 Libraries Guide for HDL Designs16 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2About UnimacrosThis section describes the unimacros that can be used with this architecture. The uimacros are organizedalphabetically.The following information is provided for each unimacro, where applicable:• Name of element• Brief description• Schematic symbol• Logic table (if any)• Port descriptions• Design Entry Method• Available attributes• Example instantiation code• For more informationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 17

Chapter 2: About UnimacrosBRAM_SDP_MACROMacro: Simple Dual Port RAMIntroductionFPGA devices contain several block RAM memories that can be configured as general-purpose 36kb or 18kbRAM/ROM memories. These block RAM memories offer fast and flexible storage of large amounts of on-chipdata. Both read and write operations are fully synchronous to the supplied clock(s) of the component. However,READ and WRITE ports can operate fully independently and asynchronously to each other, accessing thesame memory array. Byte-enable write operations are possible, and an optional output register can be used toreduce the clock-to-out times of the RAM.Note This element, must be configured so that read and write ports have the same width.Port DescriptionName Direction Width (Bits) FunctionOutput PortsDO Output See Configuration Table Data output bus addressed by RDADDR.Input PortsDI Input See Configuration Table Data input bus addressed by WRADDR.WRADDR,RDADDRInput See Configuration Table Write/Read address input buses.WE Input See Configuration Table Byte-Wide Write enable.Virtex-6 Libraries Guide for HDL Designs18 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosName Direction Width (Bits) FunctionWREN,RDENInput 1 Write/Read enableSSR Input 1 Output registers synchronous reset.REGCE Input 1 Output register clock enable input (valid onlywhen DO_REG=1)WRCLK,RDCLKInput 1 Write/Read clock input.Configuration TableDATA_WIDTH BRAM_SIZE ADDR WE72 - 37 36kb 9 836 - 1936kb 10418kb 918 - 1036kb 11218kb 109 - 536kb 12118kb 114 - 336kb 13118kb 12236kb 14118kb 13136kb 15118kb 14Design Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the ConfigurationTable above to correctly configure it to meet your design needs.InstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedAvailable AttributesAttribute Type Allowed Values Default DescriptionBRAM_SIZE String “18kb”, “36kb” “18kb” Configures RAM as 18kb or 36kbmemory.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 19

Chapter 2: About UnimacrosAttribute Type Allowed Values Default DescriptionDO_REG Integer 0, 1 0 A value of 1 enables to the outputregisters to the RAM enabling quickerclock-to-out from the RAM at theexpense of an added clock cycle ofread latency. A value of 0 allows aread in one clock cycle but will haveslower clock to out timing.INIT Hexadecimal Any 72-Bit Value All zeros Specifies the initial value on theoutput after configuration.READ_WIDTH,WRITE_WIDTHInteger 1-72 36 Specifies size of DI/DO bus.READ_WIDTH and WRITE_WIDTHmust be equal.INIT_FILE String 0 bit string “NONE” Name of the file containing initialvalues.SIM_COLLISION_CHECKString“ALL,”"WARNING_ONLY","GENERATE_X_ONLY","NONE”“ALL”Allows modification of the simulationbehavior if a memory collision occurs.The output is affected as follows:• "ALL" - Warning producedand affected outputs/memorylocation go unknown (X).• "WARNING_ONLY" - Warningproduced and affectedoutputs/memory retain lastvalue.• "GENERATE_X_ONLY" - Nowarning. However, affectedoutputs/memory go unknown(X).• "NONE" - No warning andaffected outputs/memory retainlast value.Note Setting this to a value otherthan "ALL" can allow problems inthe design go unnoticed duringsimulation. Care should be takenwhen changing the value of thisattribute. Please see the Synthesisand Simulation Design Guide for moreinformation.SIM_MODE String "SAFE" or "FAST" . "SAFE" This is a simulation only attribute. Itwill direct the simulation model torun in performance-oriented modewhen set to "FAST." Please see theSynthesis and Simulation Design Guidefor more information.SRVAL Hexadecimal Any 72-Bit Value All zeroes Specifies the output value of on theDO port upon the assertion of thesynchronous reset (RST) signal.INIT_00 toINIT_7FINITP_00 toINITP_0FHexadecimal Any 256-Bit Value All zeroes Allows specification of the initialcontents of the 16kb or 32kb datamemory array.Hexadecimal Any 256-Bit Value All zeroes Allows specification of the initialcontents of the 2kb or 4kb parity datamemory array.Virtex-6 Libraries Guide for HDL Designs20 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- BRAM_SDP_MACRO: Simple Dual Port RAM-- Virtex-5, Virtex-6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2BRAM_SDP_MACRO_inst : BRAM_SDP_MACROgeneric map (BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"DEVICE => "VIRTEX5" -- Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"WRITE_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")READ_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")DO_REG => 0, -- Optional output register (0 or 1)INIT_FILE => "NONE",SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",-- "GENERATE_X_ONLY" or "NONE"SIM_MODE => "SAFE", -- Simulation: "SAFE" vs "FAST",-- see "Synthesis and Simulation Design Guide" for detailsSRVAL => X"000000000000000000", -- Set/Reset value for port outputINIT => X"000000000000000000", -- Initial values on output port-- The following INIT_xx declarations specify the initial contents of the RAMINIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 21

Chapter 2: About UnimacrosINIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",-- The next set of INIT_xx are valid when configured as 36KbINIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",Virtex-6 Libraries Guide for HDL Designs22 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosINIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",-- The next set of INITP_xx are for the parity bitsINITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",-- The next set of INIT_xx are valid when configured as 36KbINITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")port map (DO => DO,-- Output read data portDI => DI,-- Input write data portRDADDR => RDADDR, -- Input read addressRDCLK => RDCLK, -- Input read clockRDEN => RDEN, -- Input read port enableREGCE => REGCE, -- Input read output register enableRST => RST, -- Input resetWE => WE,-- Input write enableWRADDR => WRADDR, -- Input write addressWRCLK => WRCLK, -- Input write clockWREN => WREN -- Input write port enable);-- End of BRAM_SDP_MACRO_inst instantiationVerilog Instantiation Template// BRAM_SDP_MACRO: Simple Dual Port RAM// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2BRAM_SDP_MACRO #(.BRAM_SIZE("18Kb"), // Target BRAM, "18Kb" or "36Kb".DEVICE("VIRTEX5"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6".WRITE_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb").READ_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb").DO_REG(0), // Optional output register (0 or 1).INIT_FILE ("NONE"),.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",// "GENERATE_X_ONLY" or "NONE".SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details.SRVAL(72’h000000000000000000), // Set/Reset value for port output.INIT(72’h000000000000000000), // Initial values on output port.INIT_00(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_01(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_02(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_03(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_04(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_05(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_06(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_07(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_08(256’h0000000000000000000000000000000000000000000000000000000000000000),Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 23

Chapter 2: About Unimacros.INIT_09(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_10(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_11(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_12(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_13(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_14(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_15(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_16(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_17(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_18(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_19(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_20(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_21(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_22(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_23(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_24(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_25(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_26(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_27(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_28(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_29(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_30(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_31(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_32(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_33(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_34(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_35(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_36(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_37(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_38(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_39(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3F(256’h0000000000000000000000000000000000000000000000000000000000000000),// The next set of INIT_xx are valid when configured as 36Kb.INIT_40(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_41(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_42(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_43(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_44(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_45(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_46(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_47(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_48(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_49(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4F(256’h0000000000000000000000000000000000000000000000000000000000000000),Virtex-6 Libraries Guide for HDL Designs24 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About Unimacros.INIT_50(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_51(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_52(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_53(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_54(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_55(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_56(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_57(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_58(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_59(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_60(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_61(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_62(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_63(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_64(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_65(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_66(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_67(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_68(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_69(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_70(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_71(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_72(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_73(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_74(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_75(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_76(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_77(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_78(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_79(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7F(256’h0000000000000000000000000000000000000000000000000000000000000000),// The next set of INITP_xx are for the parity bits.INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000),// The next set of INITP_xx are valid when configured as 36Kb.INITP_08(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_09(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0F(256’h0000000000000000000000000000000000000000000000000000000000000000)) BRAM_SDP_MACRO_inst (.DO(DO),// Output read data port.DI(DI),// Input write data port.RDADDR(RDADDR), // Input read address.RDCLK(RDCLK), // Input read clockVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 25

Chapter 2: About Unimacros);.RDEN(RDEN), // Input read port enable.REGCE(REGCE), // Input read output register enable.RST(RST), // Input reset.WE(WE),// Input write enable.WRADDR(WRADDR), // Input write address.WRCLK(WRCLK), // Input write clock.WREN(WREN) // Input write port enable// End of BRAM_SDP_MACRO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs26 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosBRAM_SINGLE_MACROMacro: Single Port RAMIntroductionFPGA devices contain several block RAM memories that can be configured as general-purpose 36kb or 18kbRAM/ROM memories. These single-port, block RAM memories offer fast and flexible storage of large amountsof on-chip data. Byte-enable write operations are possible, and an optional output register can be used toreduce the clock-to-out times of the RAM.Port DescriptionName Direction Width FunctionOutput PortsDO Output See Configuration Tablebelow.Input PortsDI Input See Configuration Tablebelow.ADDR Input See Configuration Tablebelow.WE Input See Configuration Tablebelow.Data output bus addressed by ADDR.Data input bus addressed by ADDR.Address input bus.Byte-Wide Write enable.EN Input 1 Write/Read enables.RST Input 1 Output registers synchronous reset.REGCE Input 1 Output register clock enable input (valid only whenDO_REG=1)CLK Input 1 Clock input.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 27

Chapter 2: About UnimacrosConfiguration TableWRITE_WIDTH READ_WIDTH BRAM_SIZE ADDR WE36 - 1936 - 19 36kb10418-10 119 - 5 124 - 3 132 1411518 - 1036 - 19 36kb11218-10 119 - 5 124 - 3 132 141159 - 536-19 36kb12118-10 129 - 5 124 - 3 132 141154 - 336-19 36kb13118-10 139 - 5 134 - 3 132 14115236-19 36kb14118-10 149 - 5 144 - 3 142 14115Virtex-6 Libraries Guide for HDL Designs28 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosWRITE_WIDTH READ_WIDTH BRAM_SIZE ADDR WE136 - 19 36kb15118 - 10 159 - 5 153 - 4 152 1511518-109 - 54 - 32118-10 18kb109 - 5 114 - 3 122 1311418-10 18kb119 - 5 114 - 3 122 1311418-10 18kb129 - 5 124 - 3 122 1311418-10 18kb139 - 5 134 - 3 132 1311418-10 18kb149 - 5 144 - 3 142 1411421111Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 29

Chapter 2: About UnimacrosDesign Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the aboveConfiguration Table in correctly configuring this element to meet your design needs.InstantiationInferenceCORE Generator and wizardsMacro supportAvailable AttributesYesNoNoRecommendedAttribute Type Allowed Values Default DescriptionBRAM_SIZE String “18kb”, “36kb” “18kb” Configures RAM as 18kb or 36kb memory.DO_REG Integer 0, 1 0 A value of 1 enables to the output registersto the RAM enabling quicker clock-to-outfrom the RAM at the expense of an addedclock cycle of read latency. A value of 0allows a read in one clock cycle but will haveslower clock to out timing.READ_WIDTH Integer 1 - 36 1 Specifies size of output bus.WRITE_WIDTH Integer 1 - 36 1 Specifies size of input bus.INIT_FILE String 0 bit string “NONE” Name of the file containing initial values.WRITE_MODE String “READ_FIRST”,“WRITE_FIRST”,“NO_CHANGE”“WRITE_FIRST”Specifies write mode to the memoryINIT Hexadecimal Any 72-Bit Value All zeros Specifies the initial value on the output afterconfiguration.SRVAL Hexadecimal Any 72-Bit Value All zeroes Specifies the output value of on the DO portupon the assertion of the synchronous reset(RST) signal.SIM_MODE String "SAFE", "FAST" "SAFE" This is a simulation only attribute. Itwill direct the simulation model to runin performance-oriented mode whenset to "FAST." Please see the Synthesisand Simulation Design Guide for moreinformation.INIT_00 toINIT_FFINITP_00 toINITP_0FHexadecimal Any 256-Bit Value All zeroes Allows specification of the initial contents ofthe 16kb or 32kb data memory array.Hexadecimal Any 256-Bit Value All zeroes Allows specification of the initial contents ofthe 2kb or 4kb parity data memory array.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- BRAM_SINGLE_MACRO: Single Port RAM-- Virtex-5, Virtex-6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2BRAM_SINGLE_MACRO_inst : BRAM_SINGLE_MACROgeneric map (Virtex-6 Libraries Guide for HDL Designs30 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosBRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"DEVICE => "VIRTEX5", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"DO_REG => 0, -- Optional output register (0 or 1)INIT_A => X"000000000", -- Initial values on output portINIT_FILE => "NONE",WRITE_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")READ_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")SIM_MODE => "SAFE", -- Simulation: "SAFE" vs "FAST",-- see "Synthesis and Simulation Design Guide" for detailsSRVAL => X"000000000", -- Set/Reset value for port outputWRITE_MODE => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"-- The following INIT_xx declarations specify the initial contents of the RAMINIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 31

Chapter 2: About UnimacrosINIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",-- The next set of INIT_xx are valid when configured as 36KbINIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",-- The next set of INITP_xx are for the parity bitsINITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",Virtex-6 Libraries Guide for HDL Designs32 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosINITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",-- The next set of INIT_xx are valid when configured as 36KbINITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")port map (DO => DO, -- Output dataADDR => ADDR, -- Input addressCLK => CLK, -- Input clockDI => DI, -- Input data portEN => EN, -- Input RAM enableREGCE => REGCE, -- Input output register enableRST => RST, -- Input resetWE => WE -- Input write enable);-- End of BRAM_SINGLE_MACRO_inst instantiationVerilog Instantiation Template// BRAM_SINGLE_MACRO: Single Port RAM// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2BRAM_SINGLE_MACRO #(.BRAM_SIZE("18Kb"), // Target BRAM, "18Kb" or "36Kb".DEVICE("VIRTEX5"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6".DO_REG(0), // Optional output register (0 or 1).INIT(36’h000000000), // Initial values on output port.INIT_FILE ("NONE"),.WRITE_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb").READ_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb").SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details.SRVAL(36’h000000000), // Set/Reset value for port output.WRITE_MODE("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE".INIT_00(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_01(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_02(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_03(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_04(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_05(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_06(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_07(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_08(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_09(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_10(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_11(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_12(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_13(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_14(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_15(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_16(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_17(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_18(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_19(256’h0000000000000000000000000000000000000000000000000000000000000000),Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 33

Chapter 2: About Unimacros.INIT_1A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_20(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_21(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_22(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_23(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_24(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_25(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_26(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_27(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_28(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_29(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_30(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_31(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_32(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_33(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_34(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_35(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_36(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_37(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_38(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_39(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3F(256’h0000000000000000000000000000000000000000000000000000000000000000),// The next set of INIT_xx are valid when configured as 36Kb.INIT_40(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_41(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_42(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_43(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_44(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_45(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_46(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_47(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_48(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_49(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_50(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_51(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_52(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_53(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_54(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_55(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_56(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_57(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_58(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_59(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_60(256’h0000000000000000000000000000000000000000000000000000000000000000),Virtex-6 Libraries Guide for HDL Designs34 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About Unimacros.INIT_61(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_62(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_63(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_64(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_65(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_66(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_67(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_68(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_69(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_70(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_71(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_72(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_73(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_74(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_75(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_76(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_77(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_78(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_79(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7F(256’h0000000000000000000000000000000000000000000000000000000000000000),// The next set of INITP_xx are for the parity bits.INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000),// The next set of INIT_xx are valid when configured as 36Kb.INITP_08(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_09(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0F(256’h0000000000000000000000000000000000000000000000000000000000000000)) BRAM_SINGLE_MACRO_inst (.DO(DO), // Output data.ADDR(ADDR), // Input address.CLK(CLK), // Input clock.DI(DI), // Input data port.EN(EN), // Input RAM enable.REGCE(REGCE), // Input output register enable.RST(RST), // Input reset.WE(WE) // Input write enable);// End of BRAM_SINGLE_MACRO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 35

Chapter 2: About UnimacrosBRAM_TDP_MACROMacro: True Dual Port RAMIntroductionFPGA devices contain several block RAM memories that can be configured as general-purpose 36kb or 18kbRAM/ROM memories. These block RAM memories offer fast and flexible storage of large amounts of on-chipdata. Both read and write operations are fully synchronous to the supplied clock(s) of the component. However,READ and WRITE ports can operate fully independently and asynchronous to each other, accessing the samememory array. Byte-enable write operations are possible, and an optional output register can be used to reducethe clock-to-out times of the RAM.Port DescriptionName Direction Width FunctionOutput PortsDOA Output See Configuration Tablebelow.DOB Output See Configuration Tablebelow.Input PortsDIA Input See Configuration Tablebelow.Data output bus addressed by ADDRA.Data output bus addressed by ADDRB.Data input bus addressed by ADDRA.Virtex-6 Libraries Guide for HDL Designs36 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosName Direction Width FunctionDIB Input See Configuration Tablebelow.ADDRA, ADDRB Input See Configuration Tablebelow.WEA, WEB Input See Configuration Tablebelow.Data input bus addressed by ADDRB.Address input buses for Port A, B.Write enable for Port A, B.ENA, ENB Input 1 Write/Read enables for Port A, B.RSTA, RSTB Input 1 Output registers synchronous reset for Port A, B.REGCEA, REGCEB Input 1 Output register clock enable input for Port A, B (validonly when DO_REG=1)CLKA, CLKB Input 1 Write/Read clock input for Port A, B.Configuration TableWRITE_WIDTH_A/B-DIA/DIB36 - 1918 - 109 - 54 - 3READ_WIDTH_A/B-DOA/DOB BRAM_SIZE ADDRA/B WEA/B36 - 19 36Kb1018-10 119 - 5 124 - 3 132 14136 - 19 36Kb1118-10 119 - 5 124 - 3 132 14136-19 36Kb1218-10 129 - 5 124 - 3 132 14136-19 36Kb1318-10 139 - 5 134 - 3 132 141151515154211Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 37

Chapter 2: About UnimacrosWRITE_WIDTH_A/B-DIA/DIB2118-109 - 54 - 321READ_WIDTH_A/B-DOA/DOB BRAM_SIZE ADDRA/B WEA/B36-19 36Kb1418-10 149 - 5 144 - 3 142 14136-19 36Kb1518-10 159 - 5 154 - 3 152 15118-10 18Kb109 - 5 114 - 3 122 13118-10 18Kb119 - 5 114 - 3 122 13118-10 18Kb129 - 5 124 - 3 122 13118-10 18Kb139 - 5 134 - 3 132 13118-10 18Kb149 - 5 144 - 3 142 1411 1 Cascade 16 1151514141414141121111Virtex-6 Libraries Guide for HDL Designs38 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosDesign Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the ConfigurationTable above to correctly configure it to meet your design needs.InstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedAvailable AttributesAttribute(s) Type Allowed Values Default DescriptionBRAM_SIZE String “18Kb”, “36Kb” “18Kb” Configures RAM as 18Kb or 36Kb memory.DO_REG Integer 0, 1 0 A value of 1 enables to the output registers tothe RAM enabling quicker clock-to-out fromthe RAM at the expense of an added clock cycleof read latency. A value of 0 allows a read inone clock cycle but will have slower clock to outtiming.INITAny 72-Bit Value All zeros Specifies the initial value on the output afterconfiguration.INIT_FILE String 0 bit string “NONE” Name of file containing initial values.READ_WIDTH,WRITE_WIDTHSIM_COLLISION_CHECKInteger 1 - 72 36 Specifies size of DI/DO bus. READ_WIDTH andWRITE_WIDTH must be equal.String“ALL,”"WARNING_ONLY","GENERATE_X_ONLY","NONE”“ALL”Allows modification of the simulation behavior ifa memory collision occurs. The output is affectedas follows:• "ALL" - Warning produced and affectedoutputs/memory location go unknown (X).• "WARNING_ONLY" - Warning producedand affected outputs/memory retain lastvalue.• "GENERATE_X_ONLY" - No warning.However, affected outputs/memory gounknown (X).• "NONE" - No warning and affectedoutputs/memory retain last value.Note Setting this to a value other than "ALL"can allow problems in the design go unnoticedduring simulation. Care should be taken whenchanging the value of this attribute. Please seethe Synthesis and Simulation Design Guide for moreinformation.SIM_MODE String "SAFE", "FAST" . "SAFE" This is a simulation only attribute. Itwill direct the simulation model to run inperformance-oriented mode when set to "FAST."Please see the Synthesis and Simulation DesignGuide for more information.SRVAL A, SRVAL_BHexadecimalHexadecimalAny 72-Bit Value All zeroes Specifies the output value of on the DO portupon the assertion of the synchronous reset (RST)signal.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 39

Chapter 2: About UnimacrosAttribute(s) Type Allowed Values Default DescriptionINIT_00 to INIT_FFINITP_00 toINITP_0FHexadecimalHexadecimalAny 256-Bit Value All zeroes Allows specification of the initial contents of the16Kb or 32Kb data memory array.Any 256-Bit Value All zeroes Allows specification of the initial contents of the2Kb or 4Kb parity data memory array.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- BRAM_TDP_MACRO: True Dual Port RAM-- Virtex-5, Virtex-6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2BRAM_TDP_MACRO_inst : BRAM_TDP_MACROgeneric map (BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"DEVICE => "VIRTEX5", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"DOA_REG => 0, -- Optional port A output register (0 or 1)DOB_REG => 0, -- Optional port B output register (0 or 1)INIT_A => X"000000000", -- Initial values on A output portINIT_B => X"000000000", -- Initial values on B output portINIT_FILE => "NONE",READ_WIDTH_A => 0, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")READ_WIDTH_B => 0, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",-- "GENERATE_X_ONLY" or "NONE"SIM_MODE => "SAFE", -- Simulation: "SAFE" vs "FAST",-- see "Synthesis and Simulation Design Guide" for detailsSRVAL_A => X"000000000", -- Set/Reset value for A port outputSRVAL_B => X"000000000", -- Set/Reset value for B port outputWRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"WRITE_WIDTH_A => 0, -- Valid values are 1, 2, 4, 9, 18 or 36 (36 only valid when BRAM_SIZE="36Kb")WRITE_WIDTH_B => 0, -- Valid values are 1, 2, 4, 9, 18 or 36 (36 only valid when BRAM_SIZE="36Kb")-- The following INIT_xx declarations specify the initial contents of the RAMINIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",Virtex-6 Libraries Guide for HDL Designs40 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosINIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",-- The next set of INIT_xx are valid when configured as 36KbINIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 41

Chapter 2: About UnimacrosINIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",-- The next set of INITP_xx are for the parity bitsINITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",-- The next set of INIT_xx are valid when configured as 36KbINITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")port map (DOA => DOA, -- Output port-A dataDOB => DOB, -- Output port-B dataADDRA => ADDRA, -- Input port-A addressADDRB => ADDRB, -- Input port-B addressCLKA => CLKA, -- Input port-A clockCLKB => CLKB, -- Input port-B clockDIA => DIA, -- Input port-A dataDIB => DIB, -- Input port-B dataENA => ENA, -- Input port-A enableENB => ENB, -- Input port-B enableREGCEA => REGCEA, -- Input port-A output register enableREGCEB => REGCEB, -- Input port-B output register enableRSTA => RSTA, -- Input port-A resetRSTB => RSTB, -- Input port-B resetWEA => WEA, -- Input port-A write enableWEB => WEB -- Input port-B write enable);-- End of BRAM_TDP_MACRO_inst instantiationVerilog Instantiation Template// BRAM_TDP_MACRO: True Dual Port RAM// Virtex-5, Virtex-6, Spartan-6Virtex-6 Libraries Guide for HDL Designs42 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About Unimacros// Xilinx HDL Libraries Guide, version 11.2BRAM_TDP_MACRO #(.BRAM_SIZE("18Kb"), // Target BRAM: "18Kb" or "36Kb".DEVICE("VIRTEX5"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6".DOA_REG(0), // Optional port A output register (0 or 1).DOB_REG(0), // Optional port B output register (0 or 1).INIT_A(36’h0000000), // Initial values on port A output port.INIT_B(36’h00000000), // Initial values on port B output port.INIT_FILE ("NONE"),.READ_WIDTH_A (0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb").READ_WIDTH_B (0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb").SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",// "GENERATE_X_ONLY" or "NONE".SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details.SRVAL_A(36’h00000000), // Set/Reset value for port A output.SRVAL_B(36’h00000000), // Set/Reset value for port B output.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE".WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE".WRITE_WIDTH_A(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb").WRITE_WIDTH_B(0), // Valid values are 1-36 (19-36 only valid when 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Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 43

Chapter 2: About Unimacros.INIT_34(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_35(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_36(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_37(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_38(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_39(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3F(256’h0000000000000000000000000000000000000000000000000000000000000000),// The next set of INIT_xx are valid when configured as 36Kb.INIT_40(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_41(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_42(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_43(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_44(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_45(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_46(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_47(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_48(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_49(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_50(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_51(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_52(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_53(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_54(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_55(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_56(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_57(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_58(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_59(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_60(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_61(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_62(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_63(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_64(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_65(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_66(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_67(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_68(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_69(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_70(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_71(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_72(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_73(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_74(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_75(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_76(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_77(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_78(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_79(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7A(256’h0000000000000000000000000000000000000000000000000000000000000000),Virtex-6 Libraries Guide for HDL Designs44 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About Unimacros.INIT_7B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7F(256’h0000000000000000000000000000000000000000000000000000000000000000),// The next set of INITP_xx are for the parity bits.INIT_FF(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000),// The next set of INITP_xx are valid when configured as 36Kb.INITP_08(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_09(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0F(256’h0000000000000000000000000000000000000000000000000000000000000000)) BRAM_TDP_MACRO_inst (.DOA(DOA), // Output port-A data.DOB(DOB), // Output port-B data.ADDRA(ADDRA), // Input port-A address.ADDRB(ADDRB), // Input port-B address.CLKA(CLKA), // Input port-A clock.CLKB(CLKB), // Input port-B clock.DIA(DIA), // Input port-A data.DIB(DIB), // Input port-B data.ENA(ENA), // Input port-A enable.ENB(ENB), // Input port-B enable.REGCEA(REGCEA), // Input port-A output register enable.REGCEB(REGCEB), // Input port-B output register enable.RSTA(RSTA), // Input port-A reset.RSTB(RSTB), // Input port-B reset.WEA(WEA), // Input port-A write enable.WEB(WEB) // Input port-B write enable);// End of BRAM_TDP_MACRO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 45

Chapter 2: About UnimacrosFIFO_DUALCLOCK_MACROMacro: Dual Clock First-In, First-Out (FIFO) RAM BufferIntroductionFPGA devices contain several block RAM memories that can be configured as general-purpose 36kb or 18kbRAM/ROM memories. Dedicated logic in the block RAM enables you to easily implement FIFOs. The FIFOcan be configured as an 18 kb or 36 kb memory. This unimacro configures the FIFO for using independent readand writes clocks. Data is read from the FIFO on the rising edge of read clock and written to the FIFO onthe rising edge of write clock.Depending on the offset between read and write clock edges, the Empty, Almost Empty, Full and Almost Fullflags can deassert one cycle later. Due to the asynchronous nature of the clocks the simulation model only reflectsthe deassertion latency cycles listed in the User Guide.Port DescriptionName Direction Width FunctionOutput PortsALMOSTEMPTY Output 1 Almost all valid entries in FIFO have been read.ALMOSTFULL Output 1 Almost all entries in FIFO memory have been filled.DO Output SeeConfigurationTable below.EMPTY Output 1 FIFO is empty.Data output bus addressed by ADDR.FULL Output 1 All entries in FIFO memory are filled.RDCOUNT Output SeeConfigurationTable below.FIFO data read pointer.Virtex-6 Libraries Guide for HDL Designs46 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosName Direction Width FunctionRDERR Output 1 When the FIFO is empty, any additional read operationgenerates an error flag.WRCOUNT Output SeeConfigurationTable below.FIFO data write pointer.WRERR Output 1 When the FIFO is full, any additional write operationgenerates an error flag.Input PortsDI Input SeeConfigurationTable below.Data input bus addressed by ADDR.RDCLK Input 1 Clock for Read domain operation.RDEN Input 1 Read EnableRST Input 1 Asynchronous reset.WRCLK Input 1 Clock for Write domain operation.WREN Input 1 Write EnableConfiguration TableThis unimacro can be instantiated only. The unimacro is a parameterizable version of the primitive. Please usethe Configuration Table below to correctly configure the unimacro to meet design needs.DATA_WIDTH FIFO_SIZE WRCOUNT RDCOUNT72 - 37 36kb 9 936 - 1918 - 109-51-436kb 10 1018kb 9 936kb 11 1118kb 10 1036kb 12 1218kb 11 1136kb 13 1318kb 12 12Design Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the aboveConfiguration Table to correctly configure this element to meet your design needs.InstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 47

Chapter 2: About UnimacrosAvailable AttributesAttributeALMOST_EMPTY_OFFSETALMOST_FULL_OFFSETTypeAllowedValues Default DescriptionHexadecimal 13-Bit Value All zeros Setting determines the difference betweenEMPTY and ALMOSTEMPTY conditions.Must be set using hexadecimal notation.Hexadecimal 13-Bit Value All zeros Setting determines the difference betweenFULL and ALMOSTFULL conditions. Mustbe set using hexadecimal notation.DATA_WIDTH Integer 1 - 72 4 Width of DI/DO bus.FIFO_SIZE String 18kb, 36kb 18kb Configures FIFO as 18kb or 36kb memory.FIRST_WORD_FALL_THROUGHBoolean FALSE, TRUE FALSE If TRUE, the first word written into the emptyFIFO appears at the FIFO output withoutRDEN asserted.SIM_MODE String "SAFE" or"FAST""SAFE"This is a simulation only attribute. Itwill direct the simulation model to run inperformance-oriented mode when set to"FAST." Please see the Synthesis and SimulationDesign Guide for more information.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- FIFO_DUALCLOCK_MACRO: Dual-Clock First-In, First-Out (FIFO) RAM Buffer-- Virtex-5, Virtex-6-- Xilinx HDL Libraries Guide, version 11.2FIFO_DUALCLOCK_MACRO_inst : FIFO_DUALCLOCK_MACROgeneric map (DEVICE => "VIRTEX5",-- Target Device: "VIRTEX5", "VIRTEX6"ALMOST_FULL_OFFSET => X"0080", -- Sets almost full thresholdALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty thresholdDATA_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")FIFO_SIZE => "18Kb",-- Target BRAM, "18Kb" or "36Kb"FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to TRUE or FALSESIM_MODE => "SAFE") -- Simulation "SAFE" vs "FAST",-- see "Synthesis and Simulation Design Guide" for detailsport map (ALMOSTEMPTY => ALMOSTEMPTY, -- Output almost emptyALMOSTFULL => ALMOSTFULL, -- Output almost fullDO => DO,-- Output dataEMPTY => EMPTY,-- Output emptyFULL => FULL,-- Output fullRDCOUNT => RDCOUNT,-- Output read countRDERR => RDERR,-- Output read errorWRCOUNT => WRCOUNT,-- Output write countWRERR => WRERR,-- Output write errorDI => DI,-- Input dataRDCLK => RDCLK,-- Input read clockRDEN => RDEN,-- Input read enableRST => RST,-- Input resetWRCLK => WRCLK,-- Input write clockWREN => WREN-- Input write enable);-- End of FIFO_DUALCLOCK_MACRO_inst instantiationVirtex-6 Libraries Guide for HDL Designs48 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosVerilog Instantiation Template// FIFO_DUALCLOCK_MACRO: Dual Clock First-In, First-Out (FIFO) RAM Buffer// Virtex-5, Virtex-6// Xilinx HDL Libraries Guide, version 11.2FIFO_DUALCLOCK_MACRO #(.ALMOST_EMPTY_OFFSET(9’h080), // Sets the almost empty threshold.ALMOST_FULL_OFFSET(9’h080), // Sets almost full threshold.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb").DEVICE("VIRTEX5"), // Target device: "VIRTEX5", "VIRTEX6".FIFO_SIZE ("18Kb"), // Target BRAM: "18Kb" or "36Kb".FIRST_WORD_FALL_THROUGH ("FALSE"), // Sets the FIFO FWFT to "TRUE" or "FALSE".SIM_MODE("SAFE") // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details) FIFO_DUALCLOCK_MACRO (.ALMOSTEMPTY(ALMOSTEMPTY), // Output almost empty.ALMOSTFULL(ALMOSTFULL), // Output almost full.DO(DO),// Output data.EMPTY(EMPTY),// Output empty.FULL(FULL),// Output full.RDCOUNT(RDCOUNT),// Output read count.RDERR(RDERR),// Output read error.WRCOUNT(WRCOUNT),// Output write count.WRERR(WRERR),// Output write error.DI(DI),// Input data.RDCLK(RDCLK),// Input read clock.RDEN(RDEN),// Input read enable.RST(RST),// Input reset.WRCLK(WRCLK),// Input write clock.WREN(WREN)// Input write enable);// End of FIFO_DUALCLOCK_MACRO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 49

Chapter 2: About UnimacrosFIFO_SYNC_MACROMacro: Synchronous First-In, First-Out (FIFO) RAM BufferIntroductionFPGA devices contain several block RAM memories that can be configured as general-purpose 36kb or 18kbRAM/ROM memories. Dedicated logic in the block RAM enables you to easily implement FIFOs. The FIFOcan be configured as an 18 kb or 36 kb memory. This unimacro configures the FIFO such that it uses one clockfor reading as well as writing.Port DescriptionName Direction Width FunctionOutput PortsALMOSTEMPTY Output 1 Almost all valid entries in FIFO have been read.ALMOSTFULL Output 1 Almost all entries in FIFO memory have beenfilled.DO Output See ConfigurationTable.EMPTY Output 1 FIFO is empty.Data output bus addressed by ADDR.FULL Output 1 All entries in FIFO memory are filled.RDCOUNT Output See ConfigurationTable below.FIFO data read pointer.RDERR Output 1 When the FIFO is empty, any additional readoperation generates an error flag.WRCOUNT Output See ConfigurationTable.FIFO data write pointer.Virtex-6 Libraries Guide for HDL Designs50 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosName Direction Width FunctionWRERR Output 1 When the FIFO is full, any additional writeoperation generates an error flag.Input PortsCLK Input 1 Clock for Read/Write domain operation.DI Input See ConfigurationTable.RDEN Input 1 Read EnableData input bus addressed by ADDR.RST Input 1 Asynchronous reset.WREN Input 1 Write EnableConfiguration TableThis unimacro can be instantiated only. The unimacro is a parameterizable version of the primitive. Please usethe configuration table below to correctly configure the unimacro to meet design needs.DATA_WIDTH FIFO_SIZE WRCOUNT RDCOUNT72 - 37 36kb 9 936 - 1918 - 109-51-436kb 10 1018kb 9 936kb 11 1118kb 10 1036kb 12 1218kb 11 1136kb 13 1318kb 12 12Design Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the aboveConfiguration Table to correctly configure this element to meet your design needs.InstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 51

Chapter 2: About UnimacrosAvailable AttributesAttributeALMOST_EMPTY_OFFSETALMOST_FULL_OFFSETTypeHexadecimalHexadecimalAllowedValues Default DescriptionAny 13-BitValueAny 13-BitValueAll zerosAll zerosDATA_WIDTH Integer 1 - 72 4 Width of DI/DO bus.Setting determines the difference between EMPTYand ALMOSTEMPTY conditions. Must be set usinghexadecimal notation.Setting determines the difference between FULLand ALMOSTFULL conditions. Must be set usinghexadecimal notation.DO_REG Binary 0,1 1 DO_REG must be set to 0 for flags and data tofollow a standard synchronous FIFO operation.When DO_REG is set to 1, effectively a pipelineregister is added to the output of the synchronousFIFO. Data then has a one clock cycle latency.However, the clock-to-out timing is improved.FIFO_SIZE String 18kb, 36kb 18kb Configures FIFO as 18kb or 36kb memory.SIM_MODE String "SAFE" or"FAST""SAFE"This is a simulation only attribute. It will direct thesimulation model to run in performance-orientedmode when set to "FAST." Please see the Synthesisand Simulation Design Guide for more information.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- FIFO_SYNC_MACRO: Synchronous First-In, First-Out (FIFO) RAM Buffer-- Virtex-5, Virtex-6-- Xilinx HDL Libraries Guide, version 11.2FIFO_SYNC_MACRO_inst : FIFO_SYNC_MACROgeneric map (DEVICE => "VIRTEX5",-- Target Device: "VIRTEX5, "VIRTEX6"ALMOST_FULL_OFFSET => X"0080", -- Sets almost full thresholdALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty thresholdDATA_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")FIFO_SIZE => "18Kb,-- Target BRAM, "18Kb" or "36Kb"SIM_MODE => "SAFE") -- Simulation) "SAFE" vs "FAST",-- see "Synthesis and Simulation Design Guide" for detailsport map (ALMOSTEMPTY => ALMOSTEMPTY, -- Output almost emptyALMOSTFULL => ALMOSTFULL, -- Output almost fullDO => DO,-- Output dataEMPTY => EMPTY,-- Output emptyFULL => FULL,-- Output fullRDCOUNT => RDCOUNT,-- Output read countRDERR => RDERR,-- Output read errorWRCOUNT => WRCOUNT,-- Output write countWRERR => WRERR,-- Output write errorCLK => CLK,-- Input clockDI => DI,-- Input dataRDEN => RDEN,-- Input read enableRST => RST,-- Input resetWREN => WREN-- Input write enable);-- End of FIFO_SYNC_MACRO_inst instantiationVirtex-6 Libraries Guide for HDL Designs52 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosVerilog Instantiation Template// FIFO_SYNC_MACRO: Synchronous First-In, First-Out (FIFO) RAM Buffer// Virtex-5, Virtex-6// Xilinx HDL Libraries Guide, version 11.2FIFO_SYNC_MACRO #(.DEVICE("VIRTEX5"), // Target Device: "VIRTEX5".ALMOST_EMPTY_OFFSET(9’h080), // Sets the almost empty threshold.ALMOST_FULL_OFFSET(9’h080), // Sets almost full threshold.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb").DEVICE("VIRTEX5"), // Target device: "VIRTEX5", "VIRTEX6".DO_REG(0), // Optional output register (0 or 1).FIFO_SIZE ("18Kb"), // Target BRAM: "18Kb" or "36Kb".SIM_MODE("SAFE") // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details) FIFO_SYNC_MACRO_inst (.ALMOSTEMPTY(ALMOSTEMPTY), // Output almost empty.ALMOSTFULL(ALMOSTFULL), // Output almost full.DO(DO),// Output data.EMPTY(EMPTY),// Output empty.FULL(FULL),// Output full.RDCOUNT(RDCOUNT),// Output read count.RDERR(RDERR),// Output read error.WRCOUNT(WRCOUNT),// Output write count.WRERR(WRERR),// Output write error.CLK(CLK),// Input clock.DI(DI),// Input data.RDEN(RDEN),// Input read enable.RST(RST),// Input reset.WREN(WREN)// Input write enable);// End of FIFO_SYNC_MACRO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 53

Chapter 2: About UnimacrosADDMACC_MACROMacro: Adder/Multiplier/AccumulatorIntroductionThe ADDMACC _MACRO simplifies the instantiation of the DSP48 block when used as a pre-add, multiplyaccumulate function. It features parameterizable input and output widths and latency that ease the integration ofDSP48 block into HDL.Port DescriptionName Direction Width FunctionOutput PortsPRODUCT Output Variable width, equals the valueof the WIDTH_A attibute plus thevalue of the WIDTH_B attribute.Input PortsPREADD1 Input Variable, see WIDTH_PREADDattribute.PREADD2 Input Variable, see WIDTH_PREADDattribute.MULTIPLIER Input Variable, seeWIDTH_MULTIPLIER attribute.Primary data output.Preadder data input.Preadder data inputMultiplier data inputCARRYIN Input 1 Carry inputCLK Input 1 ClockCE Inupt 1 Clock enableLOAD Input 1 LoadLOAD_DATA Input Variable, see WIDTH_PRODUCTattribute.RST Input 1 Synchronous ResetIn a DSP slice, when LOAD is asserted, loads Pwith A*B+LOAD_DATA.Virtex-6 Libraries Guide for HDL Designs54 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosDesign Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive.InstantiationInferenceCORE Generator and wizardsMacro supportAvailable AttributesYesNoNoRecommendedAttribute Type Allowed Values Default DescriptionWIDTH_PREADD Integer 1 to 24 24 Controls the width of PREADD1and PREADD2 inputs.WIDTH_MULTIPLIER Integer 1 to 18 18 Controls the width of MULTIPLIERinput.WIDTH_PRODUCT Integer 1 to 48 48 Controls the width of MULTIPLIERoutput.LATENCY Integer 0, 1, 2, 3, 4 3 Number of pipeline registersDEVICE String “VIRTEX6”,“SPARTAN6”“VIRTEX6”• 1 - MREG == 1• 2 - AREG == BREG == 1 andMREG == 1 or MREG == 1 andPREG == 1• 3 - AREG == BREG == 1 andMREG == 1 and PREG == 1• 4 - AREG == BREG == 2 andMREG == 1 and PREG == 1Target hardware architecture.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- ADDMACC_MACRO: Add and Multiple Accumulate Function implemented in a DSP48E-- Virtex-6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2ADDMACC_MACRO_inst : ADDMACC_MACROgeneric map (DEVICE => "VIRTEX6", -- Target Device: "VIRTEX6", "SPARTAN6"LATENCY => 3, -- Desired clock cycle latency, 1-4WIDTH_PREADD => 18, -- Pre-Adder input bus width, 1-25WIDTH_MULTIPLIER => 18, -- Multiplier input bus width, 1-18WIDTH_PRODUCT => 48) -- Product output bus width, 1-48port map (PRODUCT => PRODUCT, -- ADDMACC ouput bus, width determined by WIDTH_PRODUCT genericMULTIPLIER => MULTIPLIER, -- MULTIPLIER input bus, width determined by WIDTH_MULTIPLIER genericPREADDER1 => PREADDER1, -- 1st Pre-Adder input bus, width determined by WIDTH_PREADDER genericPREADDER2 => PREADDER2, -- 2nd Pre-Adder input bus, width determined by WIDTH_PREADDER genericCARRYIN => CARRYIN, -- 1-bit carry-in input to accumulatorCE => CE, -- 1-bit active high input clock enableCLK => CLK, -- 1-bit positive edge clock inputLOAD => LOAD, -- 1-bit active high input load accumulator enableLOAD_DATA => LOAD_DATA, -- Load accumulator input data,Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 55

Chapter 2: About Unimacros-- width determined by WIDTH_PRODUCT genericRST => RST -- 1-bit input active high reset);-- End of ADDMACC_MACRO_inst instantiationVerilog Instantiation Template// ADDMACC_MACRO: Variable width & latency - Pre-Add -> Multiplier -> Accumulate// function implemented in a DSP48E// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2ADDMACC_MACRO #(.DEVICE("VIRTEX5"), // Target Device: "VIRTEX6", "SPARTAN6".LATENCY(2), // Desired clock cycle latency, 0-2.WIDTH_PREADD(25), // Pre-adder inputwidth, 1-25.WIDTH_MULTIPLIER(18), // Multiplier input width, 1-18.WIDTH_PRODUCT(48) // MACC output width, 1-48) ADDMACC_MACRO_inst (.PRODUCT(PRODUCT), // MACC result output, width defined by WIDTH_PRODUCT parameter.CARRYIN(CARRYIN), // 1-bit carry-in input.CLK(CLK),// 1-bit clock input.CE(CE),// 1-bit clock enable input.LOAD(LOAD),// 1-bit accumulator load input.LOAD_DATA(LOAD_DATA), // Accumulator load data input, width defined by WIDTH_PRODUCT parameter.MULTIPLIER(MULTIPLIER), // Multiplier data input, width defined by WIDTH_MULTIPLIER parameter.PREADD2(PREADD2), // Preadder data input, width defined by WIDTH_PREADD parameter.PREADD1(PREADD1), // Preadder data input, width defined by WIDTH_PREADD parameter.RST(RST)// 1-bit active high synchrnous reset);// End of ADDMACC_MACRO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs56 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosADDSUB_MACROMacro: Adder/SubtractorIntroductionThe ADDSUB _MACRO simplifies the instantiation of the DSP48 block when used as a simple adder/subtractor.It features parameterizable input and output widths and latency that ease the integration of the DSP48 block intoHDL.Port DescriptionName Direction Width (Bits) FunctionOutput PortsCARRYOUT Output 1 Carry OutRESULT Output Variable, see WIDTH attrribute. Data output bus addressed by RDADDR.Input PortsADDSUB Input 1 When high, RESULT is an addition. When low,RESULT is a subtraction.A Input Variable, see WIDTH attribute. Data input to add/sub.B Input Variable, see WIDTH_B attribute. Data input to add/subCE Input 1 Clock EnableCARRYIN Input 1 Carry InCLK Input 1 ClockRST Input 1 Synchronous ResetDesign Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 57

Chapter 2: About UnimacrosInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedAvailable AttributesAttribute Type Allowed Values Default DescriptionDEVICE String “VIRTEX6”,“SPARTAN6”“VIRTEX6”Target hardware architecture.LATENCY Integer 0, 1, 2 2 Number of pipeline registers.• 1 - PREG == 1• 2 - AREG == BREG == CREG ==PREGWIDTH Integer 1-48 48 A, B, and RESULT port width; internalcustomers can override B and RESULTport widths using other parametersWIDTH_B Integer 1-48 48 Port B width override.WIDTH_RESULT Integer 1-48 48 Result port width override.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- ADDSUB_MACRO: Variable width & latency - Adder / Subtrator implemented in a DSP48E-- Virtex-5, Virtex-6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2ADDSUB_MACRO_inst : ADDSUB_MACROgeneric map (DEVICE => "VIRTEX5", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"LATENCY => 2, -- Desired clock cycle latency, 0-2WIDTH => 48) -- Input / Output bus width, 1-48port map (CARRYOUT => CARRYOUT, -- 1-bit carry-out output signalRESULT => RESULT, -- Add/sub result output, width defined by WIDTH genericA => A,-- Input A bus, width defined by WIDTH genericADD_SUB => ADD_SUB, -- 1-bit add/sub input, high selects add, low selects subtractB => B,-- Input B bus, width defined by WIDTH genericCARRYIN => CARRYIN, -- 1-bit carry-in inputCE => CE,-- 1-bit clock enable inputCLK =>CLK,-- 1-bit clock inputRST => RST-- 1-bit active high synchronous reset);-- End of ADDSUB_MACRO_inst instantiationVirtex-6 Libraries Guide for HDL Designs58 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosVerilog Instantiation Template// ADDSUB_MACRO: Variable width & latency - Adder / Subtrator implemented in a DSP48E// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2ADDSUB_MACRO #(.DEVICE("VIRTEX5"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6".LATENCY(2), // Desired clock cycle latency, 0-2.WIDTH(48) // Input / output bus width, 1-48) ADDSUB_MACRO_inst (.CARRYOUT(CARRYOUT), // 1-bit carry-out output signal.RESULT(RESULT), // Add/sub result output, width defined by WIDTH parameter.A(A),// Input A bus, width defined by WIDTH parameter.ADD_SUB(ADD_SUB), // 1-bit add/sub input, high selects add, low selects subtract.B(B),// Input B bus, width defined by WIDTH parameter.CARRYIN(CARRYIN), // 1-bit carry-in input.CE(CE),// 1-bit clock enable input.CLK(CLK),// 1-bit clock input.RST(RST)// 1-bit active high synchrnous reset);// End of ADDSUB_MACRO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 59

Chapter 2: About UnimacrosCOUNTER_LOAD_MACROMacro: Loadable CounterIntroductionThe COUNTER_LOAD_MACRO simplifies the instantiation of the DSP48 block when used as dynamic loadingup/down counter. It features parameterizable output width and count by values that ease the integrationof the DSP48 block into HDL.Port DescriptionName Direction Width FunctionOutput PortsQ Output Variable, see WIDTH_DATAattribute.Input PortsCounter output.DATA Input Variable, see WIDTH_DATA Data input (two-clock latency for variable data).attribute.CE Input 1 Clock Enable.CLK Input 1 Clock.LOAD Input Variable, see WIDTH_DATAattribute.LOAD_DATA Input Variable, see WIDTH_DATAattribute.When asserted, loads the counter fromLOAD_DATA (two-clock latency).In a DSP slice, asserting the LOAD pin will forcethis data into the P register with a latency of 2clocks.DIRECTION Input 1 High for Up and Low for Down (two-clocklatency)RST Input 1 Synchronous ResetDesign Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive.Virtex-6 Libraries Guide for HDL Designs60 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedAvailable AttributesAttribute Type Allowed Values Default DescriptionDEVICE String “VIRTEX6”,“SPARTAN6”COUNT_BYHexadecimal“VIRTEX6”Target hardware architecture.Any 48 bit value. 000000000001 Count by n; takes precedence overWIDTH_DATA.WIDTH_DATA Integer 1-48 48 Specifies counter width.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- COUNTER_LOAD_MACRO: Loadable variable counter implemented in a DSP48E-- Virtex-5, Virtex-6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2COUNTER_LOAD_MACRO_inst : COUNTER_LOAD_MACROgeneric map (COUNT_BY => X"000000000001", -- Count by valueDEVICE => "VIRTEX5",-- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"WIDTH_DATA => 48) -- Counter output bus width, 1-48port map (Q => Q,-- Counter ouput, width determined by WIDTH_DATA genericCLK => CLK,-- 1-bit clock inputCE => CE,-- 1-bit clock enable inputDIRECTION => DIRECTION, -- 1-bit up/down count direction input, high is count upLOAD => LOAD,-- 1-bit active high load inputLOAD_DATA => LOAD_DATA, -- Counter load data, width determined by WIDTH_DATA genericRST => RST-- 1-bit active high synchronous reset);-- End of COUNTER_LOAD_MACRO_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 61

Chapter 2: About UnimacrosVerilog Instantiation Template// COUNTER_LOAD_MACRO: Loadable variable counter implemented in a DSP48E// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2COUNTER_LOAD_MACRO #(.COUNT_BY(48’h000000000001), // Count by value.DEVICE("VIRTEX5"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6".WIDTH_DATA(48) // Counter output bus width, 1-48) COUNTER_LOAD_MACRO_inst (.Q(Q),// Counter output, width determined by WIDTH_DATA parameter.CLK(CLK),// 1-bit clock input.CE(CE),// 1-bit clock enable input.DIRECTION(DIRECTION), // 1-bit up/down count direction input, high is count up.LOAD(LOAD),// 1-bit active high load input.LOAD_DATA(LOAD_DATA), // Counter load data, width determined by WIDTH_DATA parameter.RST(RST)// 1-bit active high synchrnous reset);// End of COUNTER_LOAD_MACRO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs62 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosCOUNTER_TC_MACROMacro: Counter with Terminal CountIntroductionThe COUNTER_TC_MACRO simplifies the instantiation of the DSP48 block when used as a terminal count,up/down counter. It features parameterizable output width, terminal count values, count by and count directionin order to ease the integration of DSP48 block into HDL.Port DescriptionName Direction Width (Bits) FunctionOutput PortsTC Output 1 Terminal count goes high when TC_VALUE isreachedQ Output Variable, see WIDTH_DATAattribute.Input PortsCounter outputCE Input 1 Clock EnableCLK Input 1 ClockRST Input 1 Synchronous ResetDesign Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive.InstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 63

Chapter 2: About UnimacrosAvailable AttributesAttribute Type Allowed Values Default DescriptionRESET_UPON_TC Boolean True, False False Specifies whether to reset the counterupon reaching terminal countDEVICE String “VIRTEX6”,“SPARTAN6”“VIRTEX6”Target hardware architecture.DIRECTION String “UP”, “DOWN” “UP” Count up versus count down.COUNT_BYTC_VALUEHexadecimalHexadecimaAny 48 bit value 000000000001 Count by n; takes precedence overWIDTH_DATAAny 48 bit value All zeros Terminal count value.WIDTH_DATA Integer 1-48 48 Specifies counter width.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- COUNTER_TC_MACRO: Counter with terminal count implemented in a DSP48E-- Virtex-5, Virtex-6-- Xilinx HDL Libraries Guide, version 11.2COUNTER_TC_MACRO_inst : COUNTER_TC_MACROgeneric map (COUNT_BY => X"000000000001", -- Count by valueDEVICE => "VIRTEX5",-- Target Device: "VIRTEX5", "VIRTEX6"DIRECTION => "UP"-- Counter direction "UP" or "DOWN"RESET_UPON_TC => FALSE, -- Reset counter upon terminal count, TRUE or FALSETC_VALUE => X"000000000000", -- Terminal count valueWIDTH_DATA => 48) -- Counter output bus width, 1-48port map (Q => Q, -- Counter ouput, width determined by WIDTH_DATA genericTC => TC, -- 1-bit terminal count output, high = terminal count is reachedCLK => CLK, -- 1-bit clock inputCE => CE, -- 1-bit clock enable inputRST(RST) -- 1-bit active high synchronous reset);-- End of COUNTER_TC_MACRO_inst instantiationVerilog Instantiation Template// COUNTER_TC_MACRO: Counter with terminal count implemented in a DSP48E// Virtex-5, Virtex-6// Xilinx HDL Libraries Guide, version 11.2COUNTER_TC_MACRO #(.COUNT_BY(48’h000000000001), // Count by value.DEVICE("VIRTEX5"),// Target Device: "VIRTEX5", "VIRTEX6".DIRECTION("UP"),// Counter direction, "UP" or "DOWN".RESET_UPON_TC("FALSE"), // Reset counter upon terminal count, "TRUE" or "FALSE".TC_VALUE(48’h000000000000), // Terminal count value.WIDTH_DATA(48) // Counter output bus width, 1-48) COUNTER_TC_MACRO_inst (.Q(Q), // Counter output bus, width determined by WIDTH_DATA parameter.TC(TC), // 1-bit terminal count output, high = terminal count is reached.CLK(CLK), // 1-bit positive edge clock input.CE(CE), // 1-bit active high clock enable input.RST(RST) // 1-bit active high synchronous reset);// End of COUNTER_TC_MACRO_inst instantiationVirtex-6 Libraries Guide for HDL Designs64 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 65

Chapter 2: About UnimacrosEQ_COMPARE_MACROMacro: Equality ComparatorIntroductionThe EQ_COMPARE_MACRO simplifies the instantiation of the DSP48 block when used as an equalitycomparator. It features parameterizable input and output widths, latencies, mask, and input sources thatease the integration of the DSP48 block into HDL.Port DescriptionName Direction Width FunctionOutput PortsQ Output 1 Active High pattern detection. Detectsmatch of DATA_IN and the selectedDYNAMIC_PATTERN gated by the MASK.Result arrives on the same cycle as P.Input PortsDATA_IN Input Variable width, equals the valueof the WIDTH attribute.DYNAMIC_PATTERN Input Variable width, equals the valueof the WIDTH attribute.CLK Input 1 ClockCE Inupt 1 Clock enableInput data to be comparedRST Input 1 Synchronous ResetDynamic data to be compared to DATA_INDesign Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive.Virtex-6 Libraries Guide for HDL Designs66 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedAvailable AttributesAttribute Type Allowed Values Default DescriptionDEVICE String “VIRTEX6”,“SPARTAN6”“VIRTEX6”Target hardware architecture.SEL_PATTERN Integer 1 to 24 24 Controls the width of PREADD1and PREADD2 inputs.MASKSTATIC_PATTERNHexadecimalHexadecimalSEL_MASK String “MASK”,“DYNAMIC_PATTERN”48’ hex all ones Mask to be used for pattern detector.48’ hex all ones Pattern to be used for patterndetector.“MASK”Selects whether to use the staticMASK or the C input for the maskof the pattern detector.WIDTH Integer 1 to 48 48 Width of DATA_IN andDYNAMIC_PATTERNLATENCY Integer 0, 1, 2, 3 2 Number of pipeline registers• 1: QREG == 1• 2: AREG == BREG == CREG ==QREG == 1• 3: AREG == BREG == 2 andCREG == QREG == 1VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- EQ_COMPARE_MACRO: Equiality Comparator implemented in a DSP48E-- Virtex-5, Virtex-6-- Xilinx HDL Libraries Guide, version 11.2EQ_COMPARE_MACRO_inst : EQ_COMPARE_MACROgeneric map (DEVICE => "VIRTEX5",-- Target Device: "VIRTEX5", "VIRTEX6"LATENCY => 2, -- Desired clock cycle latency, 0-2MASK => X"000000000000", -- Select bits to be masked, must set-- SEL_MASK = "MASK"SEL_MASK => "MASK",-- "MASK" = use MASK generic,-- "DYNAMIC_PATTERN = use DYNAMIC_PATTERN input busSEL_PATTERN => "DYNAMIC_PATTERN", -- "DYNAMIC_PATTERN" = use DYNAMIC_PATTERN input bus-- "STATIC_PATTERN" = use STATIC_PATTERN genericSTATIC_PATTERN => X"000000000000", -- Specify static pattern,-- must set SEL_PATTERN = "STATIC_PATTERNWIDTH => 48) -- Comparator output bus width, 1-48port map (Q => Q, -- 1-bit output indicating a matchCE => CE, -- 1-bit active high input clock enable inputCLK => CLK, -- 1-bit positive edge clock inputDATA_IN => DATA_IN -- Input Data Bus, width determined by WIDTH genericVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 67

Chapter 2: About UnimacrosDYNAMIC_PATTERN => DYNAMIC_PATTERN, -- Input Dynamic Match/Mask Bus, width determined by WIDTH genericRST(RST) -- 1-bit input active high reset);-- End of EQ_COMPARE_MACRO_inst instantiationVerilog Instantiation Template// EQ_COMPARE_MACRO: Equality Comparator implemented in a DSP48E// Virtex-5, Virtex-6// Xilinx HDL Libraries Guide, version 11.2EQ_COMPARE_MACRO #(.DEVICE("VIRTEX5"), // Target Device: "VIRTEX5", "VIRTEX6".LATENCY(2), // Desired clock cycle latency, 0-2.MASK(48’h000000000000), // Select bits to be masked, must set SEL_MASK="MASK".SEL_MASK("MASK"), // "MASK" = use MASK parameter,// "DYNAMIC_PATTERN" = use DYNAMIC_PATTER input bus.SEL_PATTERN("STATIC_PATTERN"), // "STATIC_PATTERN" = use STATIC_PATTERN parameter,// "DYNAMIC_PATTERN = use DYNAMIC_PATTERN input bus.STATIC_PATTERN(48’h000000000000), // Specify static pattern, must set SEL_PATTERN = "STATIC_PATTERN".WIDTH(48) // Comparator output bus width, 1-48) EQ_COMPARE_MACRO_inst (.Q(Q), // 1-bit output indicating a match);.CE(CE), // 1-bit active high input clock enable.CLK(CLK), // 1-bit positive edge clock input.DATA_IN(DATA_IN), // Input Data Bus, width determined by WIDTH parameter.DYNAMIC_PATTERN(DYNAMIC_PATTERN), // Input Dynamic Match/Mask Bus, width determined by WIDTH parameter.RST(RST) // 1-bit input active high reset// End of EQ_COMPARE_MACRO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs68 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosMACC_MACROMacro: Multiplier/AccumulatorIntroductionThe MACC_MACRO simplifies the instantiation of the DSP48 block when used in simple signedmultiplier/accumulator mode. It features parameterizable input and output widths and latencies that ease theintegration of the DSP48 block into HDL.Port DescriptionName Direction Width FunctionOutput PortsP Output Variable width, equals the valueof the WIDTH_A attibute plus thevalue of the WIDTH_B attribute.Input PortsPrimary data output.A Input Variable, see WIDTH_A attribute. Multiplier data input.B Input Variable, see WIDTH_B attribute. Multiplier data input.CARRYIN Input 1 Carry input.CE Input 1 Clock enable.CLK Input 1 Clock.LOAD Inupt 1 Load.LOAD_DATA Input Variable width, equals the valueof the WIDTH_A attibute plus thevalue of the WIDTH_B attribute.In a DSP slice, when LOAD is asserted, loads Pwith A*B+LOAD_DATA.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 69

Chapter 2: About UnimacrosName Direction Width FunctionRST Input 1 Synchronous Reset.ADDSUB Input 1 High sets accumulator in addition mode; low setsaccumulator in subtraction mode.Design Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive.InstantiationInferenceCORE Generator and wizardsMacro supportAvailable AttributesYesNoNoRecommendedAttribute Type Allowed Values Default DescriptionWIDTH_A Integer 1 to 25 25 Controls the width of A input.WIDTH_B Integer 1 to 18 18 Controls the width of B inputLATENCY Integer 0, 1, 2, 3, 4 3 Number of pipeline registersDEVICE String “VIRTEX6”,“SPARTAN6”VHDL Instantiation Template“VIRTEX6”• 1 - MREG == 1• 2 - AREG == BREG == 1 and MREG== 1 or MREG == 1 and PREG == 1• 3 - AREG == BREG == 1 and MREG== 1 and PREG == 1• 4 - AREG == BREG == 2 and MREG== 1 and PREG == 1Target hardware architecture.Unless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- MACC_MACRO: Multiple Accumulate Function implemented in a DSP48E-- Virtex-5, Virtex-6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2MACC_MACRO_inst : MACC_MACROgeneric map (DEVICE => "VIRTEX5", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"LATENCY => 3, -- Desired clock cycle latency, 1-4WIDTH_A => 25, -- Multiplier A-input bus width, 1-25WIDTH_B => 18, -- Multiplier B-input bus width, 1-18WIDTH_P => 48) -- Accumulator output bus width, 1-48port map (P => P, -- MACC ouput bus, width determined by WIDTH_P genericA => A, -- MACC input A bus, width determined by WIDTH_A genericADDSUB => ADDSUB, -- 1-bit add/sub input, high selects add, low selects subtractB => B,-- MACC input B bus, width determined by WIDTH_B genericCARRYIN => CARRYIN, -- 1-bit carry-in input to accumulatorCE => CE, -- 1-bit active high input clock enableCLK => CLK, -- 1-bit positive edge clock inputVirtex-6 Libraries Guide for HDL Designs70 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About Unimacros);LOAD => LOAD, -- 1-bit active high input load accumulator enableLOAD_DATA => LOAD_DATA, -- Load accumulator input data,-- width determined by WIDTH_P genericRST => RST -- 1-bit input active high reset-- End of MACC_MACRO_inst instantiationVerilog Instantiation Template// MACC_MACRO: Multiply Accumulate Function implemented in a DSP48E// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2MACC_MACRO #(.DEVICE("VIRTEX5"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6".LATENCY(3), // Desired clock cycle latency, 1-4.WIDTH_A(25), // Multiplier A-input bus width, 1-25.WIDTH_B(18), // Multiplier B-input bus width, 1-18.WIDTH_P(48) // Accumulator output bus width, 1-48) MACC_MACRO (.P(P), // MACC output bus, width determined by WIDTH_P parameter.A(A), // MACC input A bus, width determined by WIDTH_A parameter.ADDSUB(ADDSUB), // 1-bit add/sub input, high selects add, low selects subtract.B(B), // MACC input B bus, width determined by WIDTH_B parameter.CARRYIN(CARRYIN), // 1-bit carry-in input to accumulator.CE(CE), // 1-bit active high input clock enable.CLK(CLK), // 1-bit positive edge clock input.LOAD(LOAD), // 1-bit active high input load accumulator enable.LOAD_DATA(LOAD_DATA), // Load accumulator input data, width determined by WIDTH_P parameter.RST(RST) // 1-bit input active high reset);// End of MACC_MACRO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 71

Chapter 2: About UnimacrosDSP_MULT_MACROMacro: MultiplierIntroductionThe MULT_MACRO simplifies the instantiation of the DSP48 block when used as a simple signed multiplier.It features parameterizable input and output widths and latencies that ease the integration of the DSP48block into HDL.Port DescriptionName Direction Width FunctionOutput PortsP Output Variable width, equals the valueof the WIDTH_A attibute plus thevalue of the WIDTH_B attribute.Input PortsPrimary data output.A Input Variable, see WIDTH_A attribute. Multiplier data input.B Input Variable, see WIDTH_B attribute. Multiplier data input.CE Input 1 Clock Enable.CLK Input 1 Clock.RST Input 1 Synchronous Reset.Design Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive.InstantiationYesInferenceNoCORE Generator and wizardsNoMacro supportRecommendedVirtex-6 Libraries Guide for HDL Designs72 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 2: About UnimacrosAvailable AttributesAttribute Type Allowed Values Default DescriptionWIDTH_A Integer 1 to 25 25 Controls the width of A input.WIDTH_B Integer 1 to 18 18 Controls the width of B input.LATENCY Integer 0, 1, 2, 3, 4 3 Number of pipeline registersDEVICE String “VIRTEX6”,“SPARTAN6”“VIRTEX6”• 1 - MREG == 1• 2 - AREG == BREG == 1 and MREG== 1 or MREG == 1 and PREG == 1• 3 - AREG == BREG == 1 and MREG== 1 and PREG == 1• 4 - AREG == BREG == 2 and MREG== 1 and PREG == 1Target hardware architecture.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- MULT_MACRO: Multiply Function implemented in a DSP48E-- Virtex-5, Virtex-6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2MULT_MACRO_inst : MULT_MACROgeneric map (DEVICE => "VIRTEX5", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"LATENCY => 3, -- Desired clock cycle latency, 0-4WIDTH_A => 18, -- Multiplier A-input bus width, 1-25WIDTH_B => 18) -- Multiplier B-input bus width, 1-18port map (P => P, -- Multiplier ouput bus, width determined by WIDTH_P genericA => A, -- Multiplier input A bus, width determined by WIDTH_A genericB => B, -- Multiplier input B bus, width determined by WIDTH_B genericCE => CE, -- 1-bit active high input clock enableCLK => CLK, -- 1-bit positive edge clock inputRST => RST -- 1-bit input active high reset);-- End of MULT_MACRO_inst instantiationVerilog Instantiation Template// MULT_MACRO: Multiply Function implemented in a DSP48E// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2MULT_MACRO #(.DEVICE("VIRTEX5"), // Target Device: ""VIRTEX5", "VIRTEX6", "SPARTAN6".LATENCY(3), // Desired clock cycle latency, 0-4.WIDTH_A(18), // Multiplier A-input bus width, 1-25.WIDTH_B(18), // Multiplier B-input bus width, 1-18) MULT_MACRO (.P(P), // Multiplier output bus, width determined by WIDTH_P parameter.A(A), // Multiplier input A bus, width determined by WIDTH_A parameter.B(B), // Multiplier input B bus, width determined by WIDTH_B parameter.CE(CE), // 1-bit active high input clock enable.CLK(CLK), // 1-bit positive edge clock input.RST(RST) // 1-bit input active high reset);Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 73

Chapter 2: About Unimacros// End of MULT_MACRO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs74 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 3Functional CategoriesThis section categorizes, by function, the circuit design elements described in detail later in this guide. Theelements ( primitives and macros) are listed in alphanumeric order under each functional category.Advanced Convenience Primitives RAM/ROMArithmetic Functions Gigabit I/O Registers/LatchesClock Components I/O Components Shift Register LUTConfig/BSCAN Components Logic Slice/CLB PrimitivesAdvancedDesign ElementPCIE_2_0SYSMONTEMAC_SINGLEDescriptionPrimitive: PCI Express version 2.0 Compliant.Primitive: System MonitorPrimitive: Tri-mode Ethernet Media Access Controller (MAC)Arithmetic FunctionsDesign ElementDSP48E1DescriptionPrimitive: 25x18 Two’s Complement Multiplier with Integrated 48-Bit, 3-InputAdder/Subtracter/Accumulator or 2-Input Logic UnitVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 75

Chapter 3: Functional CategoriesClock ComponentsDesign ElementBUFGBUFGCEBUFGCTRLBUFGMUX_CTRLBUFHBUFHCEBUFIOBUFIODQSBUFRIBUFDSIBUFDS_GTHE1IBUFDS_GTXE1MMCM_ADVDescriptionConvenience Primitive: Global Clock BufferConvenience Primitive: Global Clock Buffer with Clock EnablePrimitive: Global Clock MUX BufferConvenience Primitive: 2-to-1 Global Clock MUX BufferConvenience Primitive: Clock buffer for a single clocking regionPrimitive: Clock buffer for a single clocking region with clock enablePrimitive: Local Clock Buffer for I/OPrimitive: Differential Clock Input for Transceiver Reference ClocksPrimitive: Regional Clock Buffer for I/O and Logic ResourcesPrimitive: Differential Signaling Input BufferPrimitive: Differential Clock Input for the GTH Transceiver Reference ClocksPrimitive: Differential Clock Input for the Transceiver Reference ClocksPrimitive: MMCM is a mixed signal block designed to support clock network deskew,frequency synthesis, and jitter reduction.Config/BSCAN ComponentsDesign ElementBSCAN_VIRTEX6CAPTURE_VIRTEX6DNA_PORTEFUSE_USRFRAME_ECC_VIRTEX6ICAP_VIRTEX6STARTUP_VIRTEX6USR_ACCESS_VIRTEX6DescriptionPrimitive: Virtex®-6 JTAG Boundary-Scan Logic Access CircuitPrimitive: Virtex®-6 Readback Register Capture ControlPrimitive: Device DNA Data Access PortPrimitive: 32-bit non-volatile design IDPrimitive: Virtex®-6 Configuration Frame Error Detection and Correction CircuitryPrimitive: Internal Configuration Access PortPrimitive: Virtex®-6 Configuration Start-Up Sequence InterfacePrimitive: Virtex-6 User Access RegisterVirtex-6 Libraries Guide for HDL Designs76 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 3: Functional CategoriesConvenience PrimitivesDesign ElementBUFGBUFGCEDescriptionConvenience Primitive: Global Clock BufferConvenience Primitive: Global Clock Buffer with Clock EnableBUFGCE_1 Convenience Primitive: Global Clock Buffer with Clock Enable and Output State 1BUFGMUXConvenience Primitive: Global Clock MUX BufferBUFGMUX_1 Convenience Primitive: Global Clock MUX Buffer with Output State 1BUFGMUX_CTRLBUFGPBUFHMMCM_BASEConvenience Primitive: 2-to-1 Global Clock MUX BufferConvenience Primitive: Primary Global Buffer for Driving Clocks or LonglinesConvenience Primitive: Clock buffer for a single clocking regionConvenience Primitive: Mixed signal block designed to support clock network deskew,frequency synthesis, and jitter reduction.Gigabit I/ODesign ElementGTHE1_QUADGTXE1DescriptionPrimitive: Gigabit TransceiverPrimitive: Gigabit TransceiverI/O ComponentsDesign ElementDCIRESETIBUFIBUFDSIBUFGIBUFGDSIOBUFIOBUFDSIODELAYE1ISERDESE1KEEPEROBUFOBUFDSOBUFTDSOSERDESE1PULLDOWNPULLUPDescriptionPrimitive: DCI State Machine Reset (After Configuration Has Been Completed)Primitive: Input BufferPrimitive: Differential Signaling Input BufferPrimitive: Dedicated Input Clock BufferPrimitive: Differential Signaling Dedicated Input Clock Buffer and Optional DelayPrimitive: Bi-Directional BufferPrimitive: 3-State Differential Signaling I/O Buffer with Active Low Output EnablePrimitive: Input and Output Fixed or Variable Delay ElementPrimitive: Input SERial/DESerializerPrimitive: KEEPER SymbolPrimitive: Output BufferPrimitive: Differential Signaling Output BufferPrimitive: 3-State Output Buffer with Differential Signaling, Active-Low OutputEnablePrimitive: Dedicated IOB Output SerializerPrimitive: Resistor to GND for Input Pads, Open-Drain, and 3-State OutputsPrimitive: Resistor to VCC for Input PADs, Open-Drain, and 3-State OutputsVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 77

Chapter 3: Functional CategoriesLogicDesign ElementAND2B1LOR2LDescriptionPrimitive: Two input AND gate implemented in place of a Slice LatchPrimitive: Two input OR gate implemented in place of a Slice LatchRAM/ROMDesign ElementFIFO18E1FIFO36E1RAM128X1DRAM256X1SRAM32MRAM32X1SRAM64MRAM64X1DRAM64X1SRAMB18E1RAMB36E1DescriptionPrimitive: 18 k-bit FIFO (First In, First Out) Block RAM MemoryPrimitive: 36 kb FIFO (First In, First Out) Block RAM MemoryPrimitive: 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)Primitive: 256-Deep by 1-Wide Random Access Memory (Select RAM)Primitive: 32-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM)Primitive: 32-Deep by 1-Wide Static Synchronous RAMPrimitive: 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)Primitive: 64-Deep by 1-Wide Dual Port Static Synchronous RAMPrimitive: 64-Deep by 1-Wide Static Synchronous RAMPrimitive: 18K-bit Configurable Synchronous Block RAMPrimitive: 36K-bit Configurable Synchronous Block RAMRegisters/LatchesDesign ElementFDCEFDPEFDREFDSEIDDRIDDR_2CLKLDCELDPEODDRDescriptionPrimitive: D Flip-Flop with Clock Enable and Asynchronous ClearPrimitive: D Flip-Flop with Clock Enable and Asynchronous PresetPrimitive: D Flip-Flop with Clock Enable and Synchronous ResetPrimitive: D Flip-Flop with Clock Enable and Synchronous SetPrimitive: Input Dual Data-Rate RegisterPrimitive: Input Dual Data-Rate Register with Dual Clock InputsPrimitive: Transparent Data Latch with Asynchronous Clear and Gate EnablePrimitive: Transparent Data Latch with Asynchronous Preset and Gate EnablePrimitive: Dedicated Dual Data Rate (DDR) Output RegisterShift Register LUTDesign ElementSRL16ESRLC32EDescriptionPrimitive: 16-Bit Shift Register Look-Up Table (LUT) with Clock EnablePrimitive: 32 Clock Cycle, Variable Length Shift Register Look-Up Table (LUT) withClock EnableVirtex-6 Libraries Guide for HDL Designs78 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 3: Functional CategoriesSlice/CLB PrimitivesDesign ElementCARRY4CFGLUT5LUT5LUT5_DLUT5_LLUT6LUT6_2LUT6_DLUT6_LMUXF7MUXF7_DMUXF7_LMUXF8MUXF8_DMUXF8_LDescriptionPrimitive: Fast Carry Logic with Look AheadPrimitive: 5-input Dynamically Reconfigurable Look-Up Table (LUT)Primitive: 5-Input Lookup Table with General OutputPrimitive: 5-Input Lookup Table with General and Local OutputsPrimitive: 5-Input Lookup Table with Local OutputPrimitive: 6-Input Lookup Table with General OutputPrimitive: Six-input, 2-output, Look-Up TablePrimitive: 6-Input Lookup Table with General and Local OutputsPrimitive: 6-Input Lookup Table with Local OutputPrimitive: 2-to-1 Look-Up Table Multiplexer with General OutputPrimitive: 2-to-1 Look-Up Table Multiplexer with Dual OutputPrimitive: 2-to-1 look-up table Multiplexer with Local OutputPrimitive: 2-to-1 Look-Up Table Multiplexer with General OutputPrimitive: 2-to-1 Look-Up Table Multiplexer with Dual OutputPrimitive: 2-to-1 Look-Up Table Multiplexer with Local OutputVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 79

Virtex-6 Libraries Guide for HDL Designs80 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4About Design ElementsThis section describes the design elements that can be used with this architecture. The design elements areorganized alphabetically.The following information is provided for each design element, where applicable:• Name of element• Brief description• Schematic symbol (if any)• Logic table (if any)• Port descriptions• Design Entry Method• Available attributes (if any)• Example instantiation code• For more informationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 81

Chapter 4: About Design ElementsAND2B1LPrimitive: Two input AND gate implemented in place of a Slice LatchIntroductionThis element allows the specification of a configurable Slice latch to take the function of a two input ANDgate with one input inverted (see Logic Table). The use of this element can reduce logic levels and increaselogic density of the part by trading off register/latch resources for logic. Xilinx suggests caution when usingthis component as it can affect register packing and density since specifying one or more AND2B1L or OR2Lcomponents in a Slice disallows the use of the remaining registers and latches.Logic TableInputsOutputsDI SRI O0 0 00 1 01 0 11 1 0Port DescriptionsPort Type Width FunctionO Output 1 Output of the AND gate.DI Input 1 Active high input that is generally connected to sourcing LUT locatedin the same Slice.SRI Input 1 Active low input that is generally source from outside of the Slice.Note To allow more than one AND2B1L or OR2B1L to be packed intoa single Slice, a common signal must be connected to this input.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs82 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsBSCAN_VIRTEX6Primitive: Virtex®-6 JTAG Boundary-Scan Logic Access CircuitIntroductionThis design element allows access to and from internal logic by the JTAG Boundary Scan logic controller. Thisallows for communication between the internal running design and the dedicated JTAG pins of the FPGA.Each instance of this design element will handle one JTAG USER instruction (USER1 through USER4) as set withthe JTAG_CHAIN attribute. To handle all four USER instuctions, instantiate four of these elements and set theJTAG_CHAIN attribute appropriately.Note For specific information on boundary scan for an architecture, see the Programmable Logic Data Sheetfor this element.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 83

Chapter 4: About Design ElementsPort DescriptionsPort Type Width FunctionCAPTURE Output 1 Active upon the loading of the USER instruction. Asserts High whenthe JTAG TAP controller is in the CAPTURE-DR state.DRCK Output 1 A mirror of the TCK input pin to the FPGA when the JTAG USERinstruction assigned by JTAG_CHAIN is loaded and the JTAG TAPcontroller is in the SHIFT-DR state or in the CAPTURE-DR state.RESET Output 1 Active upon the loading of the USER instruction. It asserts High whenthe JTAG TAP controller is in theTEST-LOGIC-RESET state.RUNTEST Output 1 Indicates that JTAG is in Run Test/Idle state. Asserts high when JTAGTAP controller is in RTI stateSEL Output 1 Indicates when the USER instruction has been loaded into the JTAGInstruction Register. Becomes active in the UPDATE-IR state, and staysactive until a new instruction is loaded.SHIFT Output 1 Active upon the loading of the USER instruction. It asserts High whenthe JTAG TAP controller is in the SHIFT-DR state.TCK Output 1 A mirror of the value of the TCK input pin to the FPGA.TDI Output 1 A mirror of the TDI pin.TMS Output 1 A mirror of the TMS pin.UPDATE Output 1 Active upon the loading of the USER instruction. It asserts High whenthe JTAG TAP controller is in the UPDATE-DR state.TDO Input 1 Active upon the loading of the USER instruction. External JTAG TDOpin will reflect data input to the macro’s TDO1 pin.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionDISABLE_JTAG Boolean TRUE, FALSE FALSE Attached to BSCAN_VIRTEX6 instance 1.JTAG_CHAIN Integer 1, 2, 3, 4 1 Sets the JTAG USER instruction number that this instanceof the element will handle.Virtex-6 Libraries Guide for HDL Designs84 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- BSCAN_VIRTEX6: Virtex-6 JTAG Boundary-Scan Logic Access-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2BSCAN_VIRTEX6_inst : BSCAN_VIRTEX6generic map (DISABLE_JTAG => FALSE,JTAG_CHAIN => 1)port map (-- Chain number.CAPTURE => CAPTURE, -- 1-bit Scan Data Register Capture instruction.DRCK => DRCK,-- 1-bit Scan Clock instruction. DRCK is a gated version of TCTCK, it toggles during-- the CAPTUREDR and SHIFTDR states.RESET => RESET, -- 1-bit Scan register reset instruction.RUNTEST => RUNTEST, -- 1-bit Asserted when TAP controller is in Run Test Idle state. Make sure is the-- same name as BSCAN primitive used in Spartan products.);SEL => SEL,SHIFT => SHIFT,TCK => TCK,TDI => TDI,TMS => TMS,UPDATE => UPDATE,TDO => TDO-- 1-bit Scan mode Select instruction.-- 1-bit Scan Chain Shift instruction.-- 1-bit Scan Clock. Fabric connection to TAP Clock pin.-- 1-bit Scan Chain Output. Mirror of TDI input pin to FPGA.-- 1-bit Test Mode Select. Fabric connection to TAP.-- 1-bit Scan Register Update instruction.-- 1-bit Scan Chain Input.-- End of BSCAN_VIRTEX6_inst instantiationVerilog Instantiation Template// BSCAN_VIRTEX6: Virtex-6 JTAG Boundary-Scan Logic Access// Virtex-6// Xilinx HDL Language Template, version 11.1BSCAN_VIRTEX6 #(.DISABLE_JTAG("FALSE"),.JTAG_CHAIN(1))BSCAN_VIRTEX6_inst (// Chain number..CAPTURE(CAPTURE), // 1-bit Scan Data Register Capture instruction..DRCK(DRCK),// 1-bit Scan Clock instruction. DRCK is a gated version of TCTCK, it toggles during// the CAPTUREDR and SHIFTDR states..RESET(RESET), // 1-bit Scan register reset instruction..RUNTEST(RUNTEST), // 1-bit Asserted when TAP controller is in Run Test Idle state. Make sure is the same// name as BSCAN primitive used in Spartan products.);.SEL(SEL),.SHIFT(SHIFT),.TCK(TCK),.TDI(TDI),.TMS(TMS),.UPDATE(UPDATE),.TDO(TDO)// 1-bit Scan mode Select instruction.// 1-bit Scan Chain Shift instruction.// 1-bit Scan Clock. Fabric connection to TAP Clock pin.// 1-bit Scan Chain Output. Mirror of TDI input pin to FPGA.// 1-bit Test Mode Select. Fabric connection to TAP.// 1-bit Scan Register Update instruction.// 1-bit Scan Chain Input.// End of BSCAN_VIRTEX6_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 85

Chapter 4: About Design ElementsBUFGConvenience Primitive: Global Clock BufferIntroductionThis design element is a high-fanout buffer that connects signals to the global routing resources for low skewdistribution of the signal. BUFGs are typically used on clock nets.Port DescriptionsPort Type Width FunctionI Input 1 Clock buffer outputO Output 1 Clock buffer inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- BUFG: Global Clock Buffer-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2BUFG_inst : BUFGgeneric map ()port map (O => O, -- 1-bit Clock buffer outputI => I -- 1-bit Clock buffer input);-- End of BUFG_inst instantiationVirtex-6 Libraries Guide for HDL Designs86 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// BUFG: Global Clock Buffer (source by an internal signal)// All FPGAs// Xilinx HDL Libraries Guide, version 11.2BUFG BUFG_inst (.O(O), // Clock buffer output.I(I) // Clock buffer input);// End of BUFG_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 87

Chapter 4: About Design ElementsBUFGCEConvenience Primitive: Global Clock Buffer with Clock EnableIntroductionThis design element is a global clock buffer with a single gated input. Its O output is "0" when clock enable (CE)is Low (inactive). When clock enable (CE) is High, the I input is transferred to the O output.Logic TableInputsOutputsI CE OX 0 0I 1 IDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- BUFGCE: Global Clock Buffer with Clock Enable (active high)-- Virtex4/5/6, Spartan-3/3E/3A/6-- Xilinx HDL Libraries Guide, version 11.2BUFGCE_inst : BUFGCEport map (O => O, -- Clock buffer ouptputCE => CE, -- Clock enable inputI => I -- Clock buffer input);-- End of BUFGCE_inst instantiationVirtex-6 Libraries Guide for HDL Designs88 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// BUFGCE: Global Clock Buffer with Clock Enable (active high)// Virtex-4/5/6, Spartan-3/3E/3A/6// Xilinx HDL Libraries Guide, version 11.2BUFGCE BUFGCE_inst (.O(O), // Clock buffer output.CE(CE), // Clock enable input.I(I) // Clock buffer input);// End of BUFGCE_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 89

Chapter 4: About Design ElementsBUFGCE_1Convenience Primitive: Global Clock Buffer with Clock Enable and Output State 1IntroductionThis design element is a multiplexed global clock buffer with a single gated input. Its O output is High (1) whenclock enable (CE) is Low (inactive). When clock enable (CE) is High, the I input is transferred to the O output.Logic TableInputsOutputsI CE OX 0 1I 1 IDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- BUFGCE_1: Global Clock Buffer with Clock Enable (active low)-- Virtex-4/5/6, Spartan-3/3E/3A/6-- Xilinx HDL Libraries Guide, version 11.2BUFGCE_1_inst : BUFGCE_1port map (O => O, -- Clock buffer ouptputCE => CE, -- Clock enable inputI => I -- Clock buffer input);-- End of BUFGCE_1_inst instantiationVirtex-6 Libraries Guide for HDL Designs90 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// BUFGCE_1: Global Clock Buffer with Clock Enable (active low)// Virtex-4/5/6, Spartan-3/3E/3A/6// Xilinx HDL Libraries Guide, version 11.2BUFGCE_1 BUFGCE_1_inst (.O(O), // Clock buffer output.CE(CE), // Clock enable input.I(I) // Clock buffer input);// End of BUFGCE_1_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 91

Chapter 4: About Design ElementsBUFGCTRLPrimitive: Global Clock MUX BufferIntroductionBUFGCTRL primitive is global clock buffer that is designed as a synchronous/asynchronous "glitch free" 2:1multiplexer with two clock inputs. Unlike global clock buffers that are found in previous generation of FPGAs,these clock buffers are designed with more control pins to provide a wider range of functionality and morerobust input switching. BUFGCTRL is not limited to clocking applications.Port DescriptionsPort Type Width FunctionO Output 1 Clock Output pinI Input 1 Clock Input:I0 - Clock Input PinI1 - Clock Input PinCE0, CE1 Input 1 (each) Clock Enable Input. The CE pins represent the clock enable pinfor each clock inputs and are used to select the clock inputs. Asetup/hold time must be specified when you are using the CE pinto select inputs. Failure to meet this requirement could result ina clock glitch.S0, S1 Input 1 (each) Clock Select Input. The S pins represent the clock select pin foreach clock inputs. When using the S pin as input select, there is asetup/hold time requirement. Unlike CE pins, failure to meet thisrequirement won’t result in a clock glitch. However, it can cause theoutput clock to appear one clock cycle later.IGNORE0, IGNORE1 Input 1 (each) Clock Ignore Input. IGNORE pins are used whenever a designerwants to bypass the switching algorithm executed by the BUFGCTRL.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL Designs92 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT_OUT Integer 0, 1 0 Initializes the BUFGCTRL output to the specifiedvalue after configuration.PRESELECT_I0 Boolean FALSE, TRUE FALSE If TRUE, BUFGCTRL output uses I0 input afterconfiguration.PRESELECT_I1 Boolean FALSE, TRUE FALSE If TRUE, BUFGCTRL output uses I1 input afterconfiguration.Note Both PRESELECT attributes might not be TRUE at the same time.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 93

Chapter 4: About Design ElementsBUFGMUXConvenience Primitive: Global Clock MUX BufferIntroductionBUFGMUX is a multiplexed global clock buffer that can select between two input clocks: I0 and I1. When theselect input (S) is Low, the signal on I0 is selected for output (O). When the select input (S) is High, the signal onI1 is selected for output.BUFGMUX and BUFGMUX_1 are distinguished by the state the output assumes when that output switchesbetween clocks in response to a change in its select input. BUGFMUX assumes output state 0 and BUFGMUX_1assumes output state 1.Note BUFGMUX guarantees that when S is toggled, the state of the output remains in the inactive state until thenext active clock edge (either I0 or I1) occurs.Logic TableInputsOutputsI0 I1 S OI0 X 0 I0X I1 1 I1X X ↑ 0X X ↓ 0Port DescriptionsPort Type Width FunctionI0 Input 1 Clock0 inputI1 Input 1 Clock1 inputO Output 1 Clock MUX outputS Input 1 Clock select inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL Designs94 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionCLK_SEL_TYPE String “SYNC”, “ASYNC” “SYNC” Specifies synchronous or asynchronousclock.DISABLE_VALUE String “HIGH”, “LOW” “LOW” Specifies the state the output assumeswhen switching between inputs.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- BUFGMUX: Global Clock MUX Buffer-- Spartan-6-- Xilinx HDL Libraries Guide, version 11.2BUFGMUX_inst : BUFGMUXgeneric map (CLK_SEL_TYPE => "SYNC",)port map (O => O, -- 1-bit Clock MUX outputI0 => I0, -- 1-bit Clock0 inputI1 => I1, -- 1-bit Clock1 inputS => S -- 1-bit Clock select input);-- End of BUFGMUX_inst instantiationVerilog Instantiation Template// BUFGMUX: Global Clock Buffer 2-to-1 MUX// Spartan-3/3E/3A/6// Xilinx HDL Libraries Guide, version 11.2BUFGMUX BUFGMUX_inst (.O(O), // Clock MUX output.I0(I0), // Clock0 input.I1(I1), // Clock1 input.S(S) // Clock select input);// End of BUFGMUX_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 95

Chapter 4: About Design ElementsBUFGMUX_1Convenience Primitive: Global Clock MUX Buffer with Output State 1IntroductionThis design element is a multiplexed global clock buffer that can select between two input clocks: I0 and I1.When the select input (S) is Low, the signal on I0 is selected for output (0). When the select input (S) is High, thesignal on I1 is selected for output.This design element is distinguished from BUFGMUX by the state the output assumes when that output switchesbetween clocks in response to a change in its select input. BUFGMUX assumes output state 0 and BUFGMUX_1assumes output state 1.Logic TableInputsI0 I1 S OI0 X 0 I0X I1 1 I1X X ↑ 1X X ↓ 1OutputsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- BUFGMUX_1: Global Clock Buffer 2-to-1 MUX (inverted select)-- Spartan-3/3E/3A/6-- Xilinx HDL Libraries Guide, version 11.2BUFGMUX_1_inst : BUFGMUX_1port map (O => O, -- Clock MUX outputI0 => I0, -- Clock0 inputI1 => I1, -- Clock1 inputS => S -- Clock select input);-- End of BUFGMUX_1_inst instantiationVirtex-6 Libraries Guide for HDL Designs96 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// BUFGMUX_1: Global Clock Buffer 2-to-1 MUX (inverted select)// Spartan-3/3E/3A/6// Xilinx HDL Libraries Guide, version 11.2BUFGMUX_1 BUFGMUX_1_inst (.O(O), // Clock MUX output.I0(I0), // Clock0 input.I1(I1), // Clock1 input.S(S) // Clock select input);// End of BUFGMUX_1_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 97

Chapter 4: About Design ElementsBUFGMUX_CTRLConvenience Primitive: 2-to-1 Global Clock MUX BufferIntroductionThis design element is a global clock buffer with two clock inputs, one clock output, and a select line used tocleanly select between one of two clocks driving the global clocking resource. This component is based onBUFGCTRL, with some pins connected to logic High or Low. This element uses the S pin as the select pin for the2-to-1 MUX. S can switch anytime without causing a glitch on the output clock of the buffer.Port DescriptionsPort Direction Width FunctionO Output 1 bit Clock OutputI0 Input 1 bit One of two Clock InputsI1 Input 1 bit One of two Clock InputsS Input 1 bit Select for I0 (S=0) or I1 (S=1)Clock OutputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- BUFGMUX_CTRL: Global Clock Buffer 2-to-1 MUX-- Virtex-5/6-- Xilinx HDL Libraries Guide, version 11.2BUFGMUX_CTRL_inst : BUFGMUX_CTRLport map (O => O, -- Clock MUX outputI0 => I0, -- Clock0 inputI1 => I1, -- Clock1 inputS => S -- Clock select input);-- End of BUFGMUX_CTRL_inst instantiationVirtex-6 Libraries Guide for HDL Designs98 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// BUFGMUX_CTRL: Global Clock Buffer 2-to-1 MUX// Virtex-5, Virtex-6// Xilinx HDL Libraries Guide, version 11.2BUFGMUX_CTRL BUFGMUX_CTRL_inst (.O(O), // Clock MUX output.I0(I0), // Clock0 input.I1(I1), // Clock1 input.S(S) // Clock select input);// End of BUFGMUX_CTRL_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 99

Chapter 4: About Design ElementsBUFGPConvenience Primitive: Primary Global Buffer for Driving Clocks or LonglinesIntroductionThis design element is a primary global buffer that is used to distribute high fan-out clock or control signalsthroughout in FPGA devices. It is equivalent to an IBUFG driving a BUFG.This design element provides direct access to Configurable Logic Block (CLB) and Input Output Block (IOB)clock pins and limited access to other CLB inputs. The input to a BUFGP comes only from a dedicated IOB.Because of its structure, this element can always access a clock pin directly. However, it can access only oneof the F3, G1, C3, or C1 pins, depending on the corner in which the BUFGP is placed. When the required pincannot be accessed directly from the vertical line, PAR feeds the signal through another CLB and uses generalpurpose routing to access the load pin.Design Entry MethodThis design element is only for use in schematics.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs100 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsBUFHConvenience Primitive: Clock buffer for a single clocking regionIntroductionThe BUFH primitive is provided to allow instantiation capability to access the HCLK clock buffer resources.Port DescriptionsPort Type Width FunctionI Input 1 Clock InputO Output 1 Clock OutputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoNoVHDL Instantiation Template-- BUFH: (Clock buffer for a single clocking region)-- Spartan-6-- Xilinx HDL Libraries Guide, version 11.4BUFH_inst : BUFHgeneric map ()port map (O => O, -- 1-bit Clock OutputI => I -- 1-bit Clock Input);-- End of BUFH_inst instantiationVerilog Instantiation Template// BUFH: Clock buffer for a single clocking region// Virtex-6// Xilinx HDL Language Template, version 11.4BUFH BUFH_inst (.O(O), // 1-bit The output to the BUFH.I(I) // 1-bit The input to the BUFH);// End of BUFH_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 101

Chapter 4: About Design ElementsBUFHCEPrimitive: Clock buffer for a single clocking region with clock enableIntroductionThis element is provided to allow instantiation access to HCLK clock buffer resources. In addition, it allows forpower reduction capabilities through disabling of the clock via clock enable (CE).Port DescriptionsPort Type Width FunctionCE Input 1 Enables propagation of signal from I to O. When low, sets outputto 0.I Input 1 The input to the BUFHO Output 1 The output of the BUFHDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT_OUT DECIMAL 0, 1 0 Initial output value. Also indicates Stop Low vs StopHigh behavior.VHDL Instantiation Template-- BUFHCE: Clock buffer for a single clocking region with clock enable-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.4BUFHCE_inst : BUFHCEgeneric map (INIT_OUT => 0 -- Initial output value, also indicates stop low vs stop high behavior)port map (O => O, -- 1-bit The output of the BUFHCE => CE, -- 1-bit Enables propagation of signal from I to O. When low, sets output to 0.I => I -- 1-bit The input to the BUFH);-- End of BUFHCE_inst instantiationVirtex-6 Libraries Guide for HDL Designs102 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// BUFHCE: Clock buffer for a single clocking region with clock enable// Virtex-6// Xilinx HDL Language Template, version 11.4BUFHCE #(.INIT_OUT(0) // Initial output value, also indicates stop low vs stop high behavior)BUFHCE_inst (.O(O), // 1-bit The output of the BUFH.CE(CE), // 1-bit Enables propagation of signal from I to O. When low, sets output to 0..I(I) // 1-bit The input to the BUFH);// End of BUFHCE_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 103

Chapter 4: About Design ElementsBUFIOPrimitive: Local Clock Buffer for I/OIntroductionThis design element is a clock buffer. It is simply a clock-in, clock-out buffer. It drives a dedicated clock netwithin the I/O column, independent of the global clock resources. Thus, these elements are ideally suited forsource-synchronous data capture (forwarded/receiver clock distribution). They can only be driven by clockcapable I/Os located in the same clock region. They drive the two adjacent I/O clock nets (for a total of up to threeclock regions), as well as the regional clock buffers (BUFR). These elements cannot drive logic resources (CLB,block RAM, etc.) because the I/O clock network only reaches the I/O column.Port DescriptionsPort Type Width FunctionO Output 1 Clock outputI Input 1 Clock inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- BUFIO: Clock in, clock out buffer-- Virtex-4/5/6-- Xilinx HDL Libraries Guide, version 11.2BUFIO_inst : BUFIOport map (O => O, -- Clock buffer outputI => I -- Clock buffer input);-- End of BUFIO_inst instantiationVirtex-6 Libraries Guide for HDL Designs104 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// BUFIO: Local Clock Buffer// Virtex-4/5/6// Xilinx HDL Libraries Guide, version 11.2BUFIO BUFIO_inst (.O(O), // Clock buffer output.I(I) // Clock buffer input);// End of BUFIO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 105

Chapter 4: About Design ElementsBUFIODQSPrimitive: Differential Clock Input for Transceiver Reference ClocksIntroductionThis element is the same clock buffer as BUFIO with added dedicated circuitry (ideally used for memoryapplications) to optionally remove the extra BUFIO delay and also squelch the I/O Clock after a given burstlength from the strobe.Port DescriptionsPort Type Width FunctionDQSMASK Input 1 "Squelch" the I/O clock after a given burst lengthfrom strobe.I Input 1 Clock input port.O Output 1 Clock output port.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionDQSMASK_ENABLE Boolean FALSE, TRUE FALSE Enables the squelch circuitryVHDL Instantiation Template-- BUFIODQS: Differential Clock Input for Transceiver Reference Clocks-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2BUFIODQS_inst : BUFIODQSgeneric map (DQSMASK_ENABLE => FALSE -- Enables the squelch circuitry)port map (O => O,-- 1-bit Clock output portDQSMASK => DQSMASK, -- 1-bit "squelch" the I/O clock after a given burst length from strobeI => I-- 1-bit Clock input port);-- End of BUFIODQS_inst instantiationVirtex-6 Libraries Guide for HDL Designs106 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// BUFIODQS: Differential Clock Input for Transceiver Reference Clocks// Virtex-6// Xilinx HDL Language Template, version 11.1BUFIODQS #(.DQSMASK_ENABLE("FALSE") // Enables the squelch circuitry)BUFIODQS_inst (.O(O),// 1-bit Clock output port.DQSMASK(DQSMASK), // 1-bit "squelch" the I/O clock after a given burst length from strobe.I(I)// 1-bit Clock input port);// End of BUFIODQS_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 107

Chapter 4: About Design ElementsBUFRPrimitive: Regional Clock Buffer for I/O and Logic ResourcesIntroductionThe BUFR is a clock buffer. BUFRs drive clock signals to a dedicated clock net within a clock region, independentfrom the global clock tree. BUFRs can drive the I/O logic and logic resources (CLB, block RAM, etc.) in theexisting and adjacent clock regions. BUFRs can be driven by clock capable pins or local interconnect. In addition,BUFRs are capable of generating divided clock outputs with respect to the clock input. The divide value is anInteger between one and eight. BUFRs are ideal for source-synchronous applications requiring clock domaincrossing or serial-to-parallel conversion. There are two BUFRs in a typical clock region (two regional clocknetworks). The center column does not have BUFRs.Port DescriptionsPort Type Width FunctionCE Input 1 Clock enable port. When asserted Low, this port\ndisables theoutput clock at port O. When asserted\nHigh, this port resets thecounter used to produce\nthe divided clock output.CLR Input 1 Counter reset for divided clock output. When asserted\nHigh, thisport resets the counter used to produce\nthe divided clock output.I Input 1 Clock input port. This port is the clock source port\nfor BUFR. It canbe driven by BUFIO output or local\ninterconnect.O Output 1 Clock output port. This port drives the clock tracks\nin the clockregion of the BUFR and the two adjacent\nclock regions. This portdrives FPGA fabric, and\nIOBs.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed_Values Default DescriptionBUFR_DIVIDE STRING “BYPASS”, “1”, “2”, ”3”,“4”, “5”, “6”, “7”, “8”“BYPASS”Defines whether the output clock is adivided version\nof input clock.Virtex-6 Libraries Guide for HDL Designs108 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- BUFR: Regional Clock Buffer for I/O and Logic Resources-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2BUFR_inst : BUFRgeneric map (BUFR_DIVIDE => "BYPASS", -- Defines whether the output clock is a divided version of input clock.SIM_DEVICE => "VIRTEX4")port map (O => O,-- 1-bit Clock output port. This port drives the clock tracks in the clock region of the BUFR-- and the two adjacent clock regions. This port drives FPGA fabric, and IOBs.CE => CE, -- 1-bit Clock enable port. When asserted Low, this port disables the output clock at port O.-- When asserted High, this port resets the counter used to produce the divided clock output.CLR => CLR, -- 1-bit Counter reset for divided clock output. When asserted High, this port resets the-- counter used to produce the divided clock output.I => I-- 1-bit Clock input port. This port is the clock source port for BUFR. It can be driven by-- BUFIO output or local interconnect.);-- End of BUFR_inst instantiationVerilog Instantiation Template// BUFR: Regional Clock Buffer /w Enable, Clear and Division Capabilities// Virtex-4/5, Virtex-6// Xilinx HDL Libraries Guide, version 11.2BUFR #(.BUFR_DIVIDE("BYPASS"), // "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8".SIM_DEVICE("VIRTEX4") // Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6") BUFR_inst (.O(O), // Clock buffer output.CE(CE), // Clock enable input.CLR(CLR), // Clock buffer reset input.I(I) // Clock buffer input);// End of BUFR_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 109

Chapter 4: About Design ElementsCAPTURE_VIRTEX6Primitive: Virtex®-6 Readback Register Capture ControlIntroductionThis element provides user control and synchronization over when and how the capture register (flip-flop andlatch) information task is requested. The readback function is provided through dedicated configuration portinstructions. However, without this element, the readback data is synchronized to the configuration clock.Only register (flip-flop and latch) states can be captured. Although LUT RAM, SRL, and block RAM statesare readback, they cannot be captured.An asserted high CAP signal indicates that the registers in the device are to be captured at the next Low-to-Highclock transition. By default, data is captured after every trigger when transition on CLK while CAP is asserted.To limit the readback operation to a single data capture, add the ONESHOT=TRUE attribute to this element.Port DescriptionsPort Direction Width FunctionCAP Input 1 Readback capture triggerCLK Input 1 Readback capture clockDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoConnect all inputs and outputs to the design in order to ensure proper operation.Available AttributesAttribute Type Allowed Values Default DescriptionONESHOT Boolean TRUE, FALSE TRUE Specifies the procedure for performing single readback perCAP trigger.Virtex-6 Libraries Guide for HDL Designs110 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- CAPTURE_VIRTEX6: Virtex-6 Readback Register Capture Control-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2CAPTURE_VIRTEX6_inst : CAPTURE_VIRTEX6generic map (ONESHOT => TRUE -- Specifies the procedure for performing single readback per CAP trigger.)port map (CAP => CAP, -- 1-bit Readback capture triggerCLK => CLK -- 1-bit Readback capture clock);-- End of CAPTURE_VIRTEX6_inst instantiationVerilog Instantiation Template// CAPTURE_VIRTEX6: Virtex-6 Readback Register Capture Control// Virtex-6// Xilinx HDL Language Template, version 11.1CAPTURE_VIRTEX6 #(.ONESHOT("TRUE") // Specifies the procedure for performing single readback per CAP trigger.)CAPTURE_VIRTEX6_inst (.CAP(CAP), // 1-bit Readback capture trigger.CLK(CLK) // 1-bit Readback capture clock);// End of CAPTURE_VIRTEX6_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 111

Chapter 4: About Design ElementsCARRY4Primitive: Fast Carry Logic with Look AheadIntroductionThis circuit design represents the fast carry logic for a slice. The carry chain consists of a series of four MUXesand four XORs that connect to the other logic (LUTs) in the slice via dedicated routes to form more complexfunctions. The fast carry logic is useful for building arithmetic functions like adders, counters, subtractors andadd/subs, as well as such other logic functions as wide comparators, address decoders, and some logic gates(specifically, AND and OR).Port DescriptionsPort Direction Width FunctionO Output 4 Carry chain XOR general data outCO Output 4 Carry-out of each stage of the carry chainDI Input 4 Carry-MUX data inputS Input 4 Carry-MUX select lineCYINIT Input 1 Carry-in initialization inputCI Input 1 Carry cascade inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL Designs112 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- CARRY4: Fast Carry Logic Component-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2CARRY4_inst : CARRY4port map (CO => CO,-- 4-bit carry outO => O,-- 4-bit carry chain XOR data outCI => CI,-- 1-bit carry cascade inputCYINIT => CYINIT, -- 1-bit carry initializationDI => DI,-- 4-bit carry-MUX data inS => S-- 4-bit carry-MUX select input);-- End of CARRY4_inst instantiationVerilog Instantiation Template// CARRY4: Fast Carry Logic Component// Virtex-5, Virext-5, Spartan-6// Xilinx HDL Libraries Guide, version 11.2CARRY4 CARRY4_inst (.CO(CO),// 4-bit carry out.O(O),// 4-bit carry chain XOR data out.CI(CI),// 1-bit carry cascade input.CYINIT(CYINIT), // 1-bit carry initialization.DI(DI),// 4-bit carry-MUX data in.S(S)// 4-bit carry-MUX select input);// End of CARRY4_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 113

Chapter 4: About Design ElementsCFGLUT5Primitive: 5-input Dynamically Reconfigurable Look-Up Table (LUT)IntroductionThis element is a runtime, dynamically reconfigurable, 5-input look-up table (LUT) that enables the changingof the logical function of the LUT during circuit operation. Using the CDI pin, a new INIT value can besynchronously shifted in serially to change the logical function. The O6 output pin produces the logical outputfunction, based on the current INIT value loaded into the LUT and the currently selected I0-I4 input pins.Optionally, you can use the O5 output in combination with the O6 output to create two individual 4-inputfunctions sharing the same inputs or a 5-input function and a 4-input function that uses a subset of the 5-inputlogic (see tables below). This component occupies one of the four 6-LUT components within a slice.To cascade this element, connect the CDO pin from each element to the CDI input of the next element. This willallow a single serial chain of data (32-bits per LUT) to reconfigure multiple LUTs.Port DescriptionsPort Direction Width FunctionO6 Output 1 5-LUT outputO5 Output 1 4-LUT outputI0, I1, I2, I3, I4 Input 1 LUT inputsCDO Output 1 Reconfiguration data cascaded output (optionally connect to the CDI inputof a subsequent LUT)CDI Input 1 Reconfiguration data serial inputCLK Input 1 Reconfiguration clockCE Input 1 Active high reconfiguration clock enableVirtex-6 Libraries Guide for HDL Designs114 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNo• Connect the CLK input to the clock source used to supply the reconfiguration data.• Connect the CDI input to the source of the reconfiguration data.• Connect the CE pin to the active high logic if you need to enable/disable LUT reconfiguration.• Connect the I4-I0 pins to the source inputs to the logic equation. The logic function is output on O6 and O5.• To cascade this element, connect the CDO pin from each element to the CDI input of the next element toallow a single serial chain of data to reconfigure multiple LUTs.The INIT attribute should be placed on this design element to specify the initial logical function of the LUT. Anew INIT can be loaded into the LUT any time during circuit operation by shifting in 32-bits per LUT in thechain, representing the new INIT value. Disregard the O6 and O5 output data until all 32-bits of new INIT datahas been clocked into the LUT. The logical function of the LUT changes as new INIT data is shifted into it. Datashould be shifted in MSB (INIT[31]) first and LSB (INIT[0]) last.In order to understand the O6 and O5 logical value based on the current INIT, see the table below:I4 I3 I2 I1 I0 O6 Value O5 Value1 1 1 1 1 INIT[31] INIT[15]1 1 1 1 0 INIT[30] INIT[14]. . . . . . . . .1 0 0 0 1 INIT[17] INIT[1]1 0 0 0 0 INIT[16] INIT[0]0 1 1 1 1 INIT[15] INIT[15]0 1 1 1 0 INIT[14] INIT[14]. . . . . . . . .0 0 0 0 1 INIT[1] INIT[1]0 0 0 0 0 INIT[0] INIT[0]For instance, the INIT value of FFFF8000 would represent the following logical equations:• O6 = I4 or (I3 and I2 and I1 and I0)• O5 = I3 and I2 and I1 and I0To use these elements as two, 4-input LUTs with the same inputs but different functions, tie the I4 signal to alogical one. The INIT[31:16] values apply to the logical values of the O6 output and INIT [15:0] apply to thelogical values of the O5 output.Available AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 32-bit Value All zeros Specifies the initial logical expression ofthis element.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 115

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- CFGLUT5: Reconfigurable 5-input LUT-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2CFGLUT5_inst : CFGLUT5generic map (INT => X"00000000")port map (CDO => CDO, -- Reconfiguration cascade outputO5 => O5, -- 4-LUT outputO6 => O6, -- 5-LUT outputCDI => CDI, -- Reconfiguration data inputCE => CE, -- Reconfiguration enable inputCLK => CLK, -- Clock inputI0 => I0, -- Logic data inputI1 => I1, -- Logic data inputI2 => I2, -- Logic data inputI3 => I3, -- Logic data inputI4 => I4 -- Logic data input);-- End of CFGLUT5_inst instantiationVerilog Instantiation Template// CFGLUT5: Reconfigurable 5-input LUT// Virtex-5, Virext-5, Spartan-6// Xilinx HDL Libraries Guide, version 11.2CFGLUT5 #(.INIT(32’h00000000) // Specify initial LUT contents) CFGLUT5_inst (.CDO(CDO), // Reconfiguration cascade output.O5(O5), // 4-LUT output.O6(O6), // 5-LUT output.CDI(CDI), // Reconfiguration data input.CE(CE), // Reconfiguration enable input.CLK(CLK), // Clock input.I0(I0), // Logic data input.I1(I1), // Logic data input.I2(I2), // Logic data input.I3(I3), // Logic data input.I4(I4) // Logic data input);// End of CFGLUT5_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs116 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsDCIRESETPrimitive: DCI State Machine Reset (After Configuration Has Been Completed)IntroductionThis design element is used to reset the DCI state machine after configuration has been completed.Port DescriptionsPort Type Width FunctionLOCKED Output 1 Indicates that DCI statemachine has achieved astable state after reset.RST Input 1 Invokes the DCI statemachine to start from initialstate.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- DCIRESET: DCI State Machine Reset (After Configuration Has Been Completed)-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2DCIRESET_inst : DCIRESETgeneric map ()port map (LOCKED => LOCKED, -- 1-bit Indicates that DCI state machine has achieved a stable state after reset.RST => RST -- 1-bit Invokes the DCI state machine to start from initial state.);-- End of DCIRESET_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 117

Chapter 4: About Design ElementsVerilog Instantiation Template// DCIRESET: Digital Controlled Impedance (DCI) Reset Component// Virtex-4// Xilinx HDL Libraries Guide, version 11.2DCIRESET DCIRESET_inst (.LOCKED(LOCKED), // 1-bit DCI LOCKED Output.RST(RST)// 1-bit DCI Reset Input);// End of DCIRESET_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs118 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsDNA_PORTPrimitive: Device DNA Data Access PortIntroductionThe DNA_PORT allows access to a dedicated shift register that can be loaded with the Device DNA data bits(unique ID) for a given device. In addition to shifting out the DNA data bits, this component allows for theinclusion of supplemental data bits for additional data, or allows for the DNA data to rollover (repeat DNA dataafter initial data has been shifted out). This component is primarily used in conjunction with other circuitry tobuild added copy protection for the FPGA bitstream from possible theft.Port DescriptionsPort Type Width FunctionCLK Input 1 Input clock to the shift register.DIN Input 1 User data input to the shift register.DOUT Output 1 Serial-shifted output register.READ Input 1 Synchronous load of the shift register.SHIFT Input 1 Active High shift enabled input.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoConnect all inputs and outputs to the design to ensure proper operation.To access the Device DNA data, you must first load the shift register by setting the active high READ signal forone clock cycle. After the shift register is loaded, the data can be synchronously shifted out by enabling the activehigh SHIFT input and capturing the data out the DOUT output port. Additional data can be appended to the endof the 57-bit shift register by connecting the appropriate logic to the DIN port. If DNA data rollover is desired,connect the DOUT port directly to the DIN port to allow for the same data to be shifted out after completing the57-bit shift operation. If no additional data is necessary, the DIN port can be tied to a logic zero. The attributeSIM_DNA_VALUE can be optionally set to allow for simulation of a possible DNA data sequence. By default,the Device DNA data bits are all zeros in the simulation model.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 119

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionSIM_DNA_VALUEHexadecimal57’h000000000000000 to57’h1ffffffffffffff57’h000000000000000Specifies a DNA value for simulationpurposes (the actual value is particular tothe specific device used).For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs120 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsDSP48E1Primitive: 25x18 Two’s Complement Multiplier with Integrated 48-Bit, 3-InputAdder/Subtracter/Accumulator or 2-Input Logic UnitIntroductionThis design element is a versatile, scalable, hard IP block within Virtex®-6 that allows for the creation of compact,high-speed, arithmetic-intensive operations, such as those seen for many DSP algorithms. Some of the functionscapable within the block include multiplication, addition (including pre-adder), subtraction, accumulation,shifting, logical operations, and pattern detection.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 121

Chapter 4: About Design ElementsPort DescriptionsPort Type Width FunctionA[29:0] Input 30 25-bit data input to Multiplier, Pre-adder, or 30-bit MSB Data Inputto Adder/Logic Unit.ACIN[29:0] Input 30 Cascade input for Port A. If used, connect to ACOUT of upstreamcascaded DSP slice. If not used, tie port to all zeros.ACOUT[29:0] Output 30 Cascade output for Port A. If used, connect to ACIN of downstreamcascaded DSP slice. If not used, leave unconnected.ALUMODE[3:0] Input 4 Control input to select Logic Unit functions including addition andsubtraction.B[17:0] Input 18 18-bit data input to Multiplier, or 18-bit LSB Data Input toAdder/Logic Unit.BCIN[17:0] Input 18 Cascade input for Port B. If used, connect to BCOUT of upstreamcascaded DSP slice. If not used, tie port to all zeros.BCOUT[17:0] Output 18 Cascade output for Port B. If used, connect to BCIN of downstreamcascaded DSP slice. If not used, leave unconnected.C[47:0] Input 48 48-bit data input to Adder/Logic Unit and Pattern Detector.CARRYCASCIN Input 1 Cascaded CARRYOUT from upstream DSP slice.CARRYCASCOUT Output 1 Cascaded CARRYOUT to downstream DSP slice.CARRYIN Input 1 External carry input to the Adder/Logic Unit.CARRYINSEL[2:0] Input 3 Selects carry-in source to the DSP slice.CARRYOUT[3:0] Output 4 Carry out signal for arithmetic operations (addition, subtraction,etc.).• If USE_SIMD="FOUR12", CARRYOUT represents the carry-outof each 12 bit field of the Accumulate/Adder/Logic Unit.• If USE_SIMD="TWO24" CARRYOUT and CARRYOUT representthe carry-out of each 24-bit field of the Accumulator/Adder.• If USE_SIMD="ONE48", CARRYOUT is the only valid carry outfrom the Accumulate/Adder/Logic Unit.CEAD Input 1 Active High, clock enable for pre-adder output AD pipeline register.Tie to logic one if not used and ADREG=1. Tie to logic zero ifADREG=0.CEALUMODE Input 1 Active High, clock enable for the ALUMODE input registers(ALUMODEREG=1). Tie to logic one if not used.CEA1 Input 1 Active High, clock enable for the A port registers (AREG=2). Tieto logic one if not used and AREG=2. Tie to logic zero if AREG=0or 1. When two registers are used, this is the first sequentially.When Dynamic AB Access is used, this clock enable is applied forINMODE=1.CEA2 Input 1 Active High, clock enable for the A port registers. Tie to logic one ifnot used and AREG=1 or 2. Tie to logic zero if AREG=0. When tworegisters are used, this is the second sequentially. When one registeris used (AREG=1), CEA2 is the clock enable.CEB1 Input 1 Active High, clock enable for the B port registers (BREG=2). Tieto logic one if not used and BREG=2. Tie to logic zero if BREG=0or 1. When two registers are used, this is the first sequentially.When Dynamic AB Access is used, this clock enable is applied forINMODE=1.Virtex-6 Libraries Guide for HDL Designs122 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPort Type Width FunctionCEB2 Input 1 Active High, clock enable for the B port registers. Tie to logic one ifnot used and BREG=1 or 2. Tie to logic zero if BREG=0. When tworegisters are used, this is the second sequentially. When one registeris used (BREG=1), CEB2 is the clock enable.CEC Input 1 Active High, clock enable for the C port registers (CREG=1). Tieto logic one if not used.CECARRYIN Input 1 Active High, clock enable for the carry-in registers(CARRYINREG=1). Tie to logic one if not used.CECTRL Input 1 Active High, clock enable for the OPMODE and CARRYINSELregisters. Tie to logic one if not used.CED Input 1 Active High, clock enable for the D port registers (DREG=1). Tieto logic one if not used.CEINMODE Input 1 Active High, clock enable for the INMODE input registers(INMODEREG=1). Tie to logic one if not used.CEM Input 1 Active High, clock enable for the multiplier registers (MREG=1). Tieto logic one if not used.CEP Input 1 Active High, clock enable for the output port registers (PREG=1). Tieto logic one if not used.CLK Input 1 DSP slice clock input.D[24:0] Input 25 25-bit data input to the Pre-adder or alternative input to theMultiplier.INMODE[4:0] Input 5 Control input to select the arithmetic operation of the DSP slicein conjunction with ALUMODE and OPMODE. INMODE signalscontrol the functionality of the signals and blocks that precede theMultiplier (including the pre-adder).MULTSIGNIN Input 1 Multiplier sign output from upstream cascaded DSP slice. Use forthe purpose of sign extending the MACC output when greater than48-bit output. Should only be connected to the MULTSIGNOUToutput pin.MULTSIGNOUT Output 1 Multiplier sign output sent to downstream cascaded DSP slice. Usefor the purpose of sign extending the MACC output when greaterthan 48-bit output. Should only be connected to the MULTISIGNINinput pin.OPMODE[6:0] Input 7 Control input to select the arithmetic operation of the DSP slice inconjunction with ALUMODE and INMODE.OVERFLOW Output 1 Active High output detects overflow in addition/accumulate ifpattern detector is used and PREG=1.P[47:0] Output 48 Primary data output.PATTERNBDETECT Output 1 Active High pattern detection. Detects match of P and the bar of theselected PATTERN gated by the MASK. Result arrives on the samecycle as P.PATTERNDETECT Output 1 Active High pattern detection. Detects match of P and the selectedPATTERN gated by the MASK. Result arrives on the same cycle as P.PCIN[47:0] Input 48 Cascade input for Port P. If used, connect to PCOUT of upstreamcascaded DSP slice. If not used, tie port to all zeros.PCOUT[47:0] Output 48 Cascade output for Port P. If used, connect to PCIN of downstreamcascaded DSP slice. If not used, leave unconnected.RSTA Input 1 Active High, synchronous reset for the A port registers (AREG=1 or2). Tie to logic zero if not used.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 123

Chapter 4: About Design ElementsPort Type Width FunctionRSTALLCARRYIN Input 1 Active High, synchronous reset for all carry-in registers(CARRYINREG=1). Tie to logic zero if not used.RSTALUMODE Input 1 Active High, synchronous reset for the ALUMODE registers(ALUMODEREG=1). Tie to logic zero if not used.RSTB Input 1 Active High, synchronous reset for the B port registers (BREG=1 or2). Tie to logic zero if not used.RSTC Input 1 Active High, synchronous reset for the C port registers (CREG=1).Tie to logic zero if not used.RSTCTRL Input 1 Active High, synchronous reset for the OPMODE and CARRYINSELregisters (OPMODEREG=1 and CARRYINSELREG=1). Tie to logiczero if not used.RSTD Input 1 Active High, synchronous reset for the D port registers (DREG=1).Tie to logic zero if not used.RSTINMODE Input 1 Active High, synchronous reset for the INMODE registers(INMODEREG=1). Tie to logic zero if not used.RSTM Input 1 Active High, synchronous reset for the multiplier registers(MREG=1). Tie to logic zero if not used.RSTP Input 1 Active High, synchronous reset for the output registers (PREG=1).Tie to logic zero if not used.UNDERFLOW Output 1 Active High output detects underflow in addition/accumulate ifpattern detector is used and PREG = 1.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedYesYesAvailable AttributesAttribute Type Allowed Values Default DescriptionACASCREG Integer 1, 0, 2 1 In conjunction with AREG, selects the number ofA input registers on A cascade ACOUT. Must beequal to or one less than AREG value.ADREG Integer 1, 0 1 Selects usage of Pre-adder output (AD) PipelineRegisters. Set to 1 to use the AD PipelineRegisters.A_INPUT String “DIRECT”,“CASCADE”“DIRECT”Selects between A and ACIN inputs.ALUMODEREG Integer 1, 0 1 Set to 1 to register the ALUMODE inputs.AREG Integer 1, 0, 2 1 Selects whether to register the A input to theDSP48E1.Virtex-6 Libraries Guide for HDL Designs124 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionAUTORESET_PATDETString“NO_RESET”,“RESET_MATCH”,“RESET_NOT_MATCH”“NO_RESET”Automatically reset DSP slice P Register(accumulated value or Counter Value) on thenext clock cycle if pattern detect event hasoccurred on this clock cycle.If pattern is matched, or whenever pattern is notmatched on the current cycle but was matchedon the previous clock cycle, the RESET_MATCHand RESET_NOT_MATCH settings distinguishwhether the DSP slice should cause auto reset ofP Register on the next cycle.BCASCREG Integer 1, 0, 2 1 In conjunction with BREG, selects the number ofB input registers on B cascade BCOUT. Must beequal to or one less than BREG value.B_INPUT String “DIRECT”,“CASCADE”“DIRECT”Selects between B and BCIN inputs.Selectswhether to register the A input to the DSP48.BREG Integer 1, 0, 2 1 Selects whether to register the B input to theDSP48E1.CARRYINREG Integer 1, 0 1 Set to 1 to register the CARRYIN inputs.CARRYINSELREG Integer 1, 0 1 Set to 1 to register the CARRYINSEL inputs.CREG Integer 1, 0 1 Selects whether to register the C input to theDSP48E1.DREG Integer 1, 0 1 Selects whether to register the D input to theDSP48E1.INMODEREG Integer 1, 0 1 Set to 1 to register the INMODE inputs.MASK48’h000000000000 to48’hffffffffffff48’h3fffffffffffMask to be used for pattern detector.MREG Integer 1, 0 1 Selects whether to register the multiplier stage ofthe DSP48. Enable=1/disable=0.OPMODEREG Integer 1, 0 1 Set to 1 to register the OPMODE inputs.PATTERNHexadecimalHexadecimal48’h000000000000 to48’hffffffffffffAll zerosPattern to be used for pattern detector.PREG Integer 1, 0 1 Selects whether to register the P input to theDSP48E1.SEL_MASK String “MASK”, “C”,“ROUNDING_MODE1”,“ROUNDING_MODE2”“MASK”Selects mask to be used for pattern detector. Thevalues C and MASK are for standard uses of thepattern detector (counter, overflow detection,etc.). ROUNDING_MODE1 (C-bar left shifted by1) and ROUNDING_MODE2 (C-bar left shiftedby 2) select special masks based on the optionallyregistered C port. These rounding modes can beused to implement convergent rounding in theDSP slice using the pattern detector as describedin the Virtex-6 FPGA DSP48E1 Block User Guide.SEL_PATTERN String “PATTERN”, “C” “PATTERN” Selects pattern to be used for pattern detector.USE_DPORT Boolean FALSE, TRUE FALSE Selects usage of the Pre-adder and D Port.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 125

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionUSE_MULT String “MULTIPLY”,“DYNAMIC”,“NONE”USE_PATTERN_DETECTString“NO_PATDET”,“PATDET”USE_SIMD String “ONE48”,“FOUR12”,“TWO24”“MULTIPLY”Selects usage of the Multiplier. Set to NONE tosave power when using only the adder/LogicUnit. The DYNAMIC setting indicates thatthe user is switching between A*B and A:Boperations on the fly and therefore needs to getthe worst case timing of the two paths.“NO_PATDET” Set to PATDET to enable pattern detection in thesimulation model and speed files.“ONE48”Selects usage of the SIMD (Single InstructionMultiple Data) adder/Logic Unit. Selects betweenone 48-bit Logic Unit, two 24-bit Logic Units,or four 12-bit Logic Units. Note that all four12 bit Logic Units share the same Instruction(i.e. all can subtract on the same cycle or addon the same cycle). This allows the 48 bit adderto be broken up into smaller adders for lesscomputationally intensive applications. SIMDonly has an effect on arithmetic operation (add,accumulate, subtract, etc.) and has no effect onlogical operations.VHDL Instantiation Template-- DSP48E1: 25x18 Two’s Complement Multiplier with Integrated 48-Bit, 3-Input Adder/Subtracter/Accumulator or 2-Input Logic Unit-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2DSP48E1_inst : DSP48E1generic map (ACASCREG => 1,-- Number of pipeline registers between A/ACIN input and ACOUT output,-- 0, 1, or 2ADREG => 1, -- Number of pipeline registers on pre-adder output, 0 or 1ALUMODEREG => 1, -- Number of pipeline registers on ALUMODE input, 0 or 1AREG => 1, -- Number of pipeline registers on the A input, 0, 1 or 2AUTORESET_PATDET => "NO_RESET", -- NO_RESET, RESET_MATCH, RESET_NOT_MATCHA_INPUT => "DIRECT",-- Selects A input used, "DIRECT" (A port) or "CASCADE" (ACIN port)BCASCREG => 1,-- Number of pipeline registers between B/BCIN input and BCOUT output,-- 0, 1, or 2BREG => 1, -- Number of pipeline registers on the B input, 0, 1 or 2B_INPUT => "DIRECT",-- Selects B input used, "DIRECT" (B port) or "CASCADE" (BCIN port)CARRYINREG => 1, -- Number of pipeline registers for the CARRYIN input, 0 or 1CARRYINSELREG => 1, -- Number of pipeline registers for the CARRYINSEL input, 0 or 1CREG => 1, -- Number of pipeline registers on the C input, 0 or 1DREG => 1, -- Number of pipeline registers on the D input, 0 or 1INMODEREG => 1, -- Number of pipeline registers on INMODE input, 0 or 1MASK => X"3fffffffffff",-- 48-bit Mask value for pattern detectMREG => 1, -- Number of multiplier pipeline registers, 0 or 1OPMODEREG => 1, -- Number of pipeline registers on OPMODE input, 0 or 1PATTERN => X"000000000000", -- 48-bit Pattern match for pattern detectPREG => 1, -- Number of pipeline registers on the P output, 0 or 1SEL_MASK => "MASK",-- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"SEL_PATTERN => "PATTERN",-- Select pattern value between the "PATTERN" value or the value on-- the "C" portUSE_DPORT => FALSE,-- Select D port usage, TRUE or FALSEUSE_MULT => "MULTIPLY",-- Select multiplier usage, "MULTIPLY", "DYNAMIC", or "NONE" (no-- multiplier)USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect, "PATDET", "NO_PATDET"USE_SIMD => "ONE48"-- SIMD selection, "ONE48", "TWO24", "FOUR12")port map (-- Cascade: 30-bit (each) Cascade PortsACOUT => ACOUT,-- 30-bit A port cascade outputBCOUT => BCOUT,-- 18-bit B port cascade outputCARRYCASCOUT => CARRYCASCOUT, -- 1-bit cascade carry outputMULTSIGNOUT => MULTSIGNOUT, -- 1-bit multiplier sign cascade outputPCOUT => PCOUT,-- 48-bit cascade outputVirtex-6 Libraries Guide for HDL Designs126 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design Elements);-- Control: 1-bit (each) Control Inputs/Status BitsOVERFLOW => OVERFLOW,-- 1-bit overflow in add/acc outputPATTERNBDETECT => PATTERNBDETECT, -- 1-bit active high pattern bar detect outputPATTERNDETECT => PATTERNDETECT, -- 1-bit active high pattern detect outputUNDERFLOW => UNDERFLOW,-- 1-bit active high underflow in add/acc output-- Data: 4-bit (each) Data PortsCARRYOUT => CARRYOUT,-- 4-bit carry outputP => P,-- 48-bit output-- Cascade: 30-bit (each) Cascade PortsACIN => ACIN,-- 30-bit A cascade data inputBCIN => BCIN,-- 18-bit B cascade inputCARRYCASCIN => CARRYCASCIN, -- 1-bit cascade carry inputMULTSIGNIN => MULTSIGNIN,-- 1-bit multiplier sign inputPCIN => PCIN,-- 48-bit P cascade input-- Control: 4-bit (each) Control Inputs/Status BitsALUMODE => ALUMODE,-- 4-bit ALU control inputCARRYINSEL => CARRYINSEL,-- 3-bit carry select inputCEINMODE => CEINMODE,-- 1-bit active high clock enable input for INMODE registersCLK => CLK,-- 1-bit Clock inputINMODE => INMODE,-- 5-bit INMODE control inputOPMODE => OPMODE,-- 7-bit operation mode inputRSTINMODE => RSTINMODE,-- 1-bit reset input for INMODE pipeline registers-- Data: 30-bit (each) Data PortsA => A,-- 30-bit A data inputB => B,-- 18-bit B data inputC => C,-- 48-bit C data inputCARRYIN => CARRYIN,-- 1-bit carry input signalD => D,-- 25-bit D data input-- Reset/Clock Enable: 1-bit (each) Reset/Clock Enable InputsCEA1 => CEA1,-- 1-bit active high clock enable input for 1st stage A registersCEA2 => CEA2,-- 1-bit active high clock enable input for 2nd stage A registersCEAD => CEAD,-- 1-bit active high clock enable input for pre-adder output registersCEALUMODE => CEALUMODE,-- 1-bit active high clock enable input for ALUMODE registersCEB1 => CEB1,-- 1-bit active high clock enable input for 1st stage B registersCEB2 => CEB2,-- 1-bit active high clock enable input for 2nd stage B registersCEC => CEC,-- 1-bit active high clock enable input for C registersCECARRYIN => CECARRYIN,-- 1-bit active high clock enable input for CARRYIN registerCECTRL => CECTRL,-- 1-bit active high clock enable input for OPMODE and carry registersCED => CED,-- 1-bit active high clock enable input for D registersCEM => CEM,-- 1-bit active high clock enable input for multiplier registersCEP => CEP,-- 1-bit active high clock enable input for P registersRSTA => RSTA,-- 1-bit reset input for A pipeline registersRSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit reset input for carry pipeline registersRSTALUMODE => RSTALUMODE,-- 1-bit reset input for ALUMODE pipeline registersRSTB => RSTB,-- 1-bit reset input for B pipeline registersRSTC => RSTC,-- 1-bit reset input for C pipeline registersRSTCTRL => RSTCTRL,-- 1-bit reset input for OPMODE pipeline registersRSTD => RSTD,-- 1-bit reset input for D pipeline registersRSTM => RSTM,-- 1-bit reset input for multiplier registersRSTP => RSTP-- 1-bit reset input for P pipeline registers-- End of DSP48E1_inst instantiationVerilog Instantiation Template// DSP48E1: 25x18 Two’s Complement Multiplier with Integrated 48-Bit, 3-Input Adder/Subtracter/Accumulator or 2-Input Logic Unit// Virtex-6// Xilinx HDL Language Template, version 11.1DSP48E1 #(.ACASCREG(1),// Number of pipeline registers between A/ACIN input and ACOUT output,// 0, 1, or 2.ADREG(1), // Number of pipeline registers on pre-adder output, 0 or 1.ALUMODEREG(1), // Number of pipeline registers on ALUMODE input, 0 or 1.AREG(1), // Number of pipeline registers on the A input, 0, 1 or 2.AUTORESET_PATDET("NO_RESET"),.A_INPUT("DIRECT"),.BCASCREG(1),// NO_RESET, RESET_MATCH, RESET_NOT_MATCH// Selects A input used, "DIRECT" (A port) or "CASCADE" (ACIN port)// Number of pipeline registers between B/BCIN input and BCOUT output,// 0, 1, or 2.BREG(1), // Number of pipeline registers on the B input, 0, 1 or 2.B_INPUT("DIRECT"),// Selects B input used, "DIRECT" (B port) or "CASCADE" (BCIN port)Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 127

Chapter 4: About Design Elements.CARRYINREG(1), // Number of pipeline registers for the CARRYIN input, 0 or 1.CARRYINSELREG(1), // Number of pipeline registers for the CARRYINSEL input, 0 or 1.CREG(1), // Number of pipeline registers on the C input, 0 or 1.DREG(1), // Number of pipeline registers on the D input, 0 or 1.INMODEREG(1), // Number of pipeline registers on INMODE input, 0 or 1.MASK(48’h3fffffffffff),// 48-bit Mask value for pattern detect.MREG(1), // Number of multiplier pipeline registers, 0 or 1.OPMODEREG(1), // Number of pipeline registers on OPMODE input, 0 or 1.PATTERN(48’h000000000000), // 48-bit Pattern match for pattern detect.PREG(1), // Number of pipeline registers on the P output, 0 or 1.SEL_MASK("MASK"),// "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2".SEL_PATTERN("PATTERN"),// Select pattern value between the "PATTERN" value or the value on the// "C" port.USE_DPORT("FALSE"),.USE_MULT("MULTIPLY"),// Select D port usage, TRUE or FALSE// Select multiplier usage, "MULTIPLY", "DYNAMIC", or "NONE" (no// multiplier).USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect, "PATDET", "NO_PATDET".USE_SIMD("ONE48")// SIMD selection, "ONE48", "TWO24", "FOUR12")DSP48E1_inst (// Cascade: 30-bit (each) Cascade Ports.ACOUT(ACOUT),// 30-bit A port cascade output.BCOUT(BCOUT),// 18-bit B port cascade output.CARRYCASCOUT(CARRYCASCOUT), // 1-bit cascade carry output.MULTSIGNOUT(MULTSIGNOUT), // 1-bit multiplier sign cascade output.PCOUT(PCOUT),// 48-bit cascade output// Control: 1-bit (each) Control Inputs/Status Bits.OVERFLOW(OVERFLOW),// 1-bit overflow in add/acc output.PATTERNBDETECT(PATTERNBDETECT), // 1-bit active high pattern bar detect output.PATTERNDETECT(PATTERNDETECT), // 1-bit active high pattern detect output.UNDERFLOW(UNDERFLOW),// 1-bit active high underflow in add/acc output// Data: 4-bit (each) Data Ports.CARRYOUT(CARRYOUT),// 4-bit carry output.P(P),// 48-bit output// Cascade: 30-bit (each) Cascade Ports.ACIN(ACIN),// 30-bit A cascade data input.BCIN(BCIN),// 18-bit B cascade input.CARRYCASCIN(CARRYCASCIN), // 1-bit cascade carry input.MULTSIGNIN(MULTSIGNIN),// 1-bit multiplier sign input.PCIN(PCIN),// 48-bit P cascade input// Control: 4-bit (each) Control Inputs/Status Bits.ALUMODE(ALUMODE),// 4-bit ALU control input.CARRYINSEL(CARRYINSEL),// 3-bit carry select input.CEINMODE(CEINMODE),// 1-bit active high clock enable input for INMODE registers.CLK(CLK),// 1-bit Clock input.INMODE(INMODE),// 5-bit INMODE control input.OPMODE(OPMODE),// 7-bit operation mode input.RSTINMODE(RSTINMODE),// 1-bit reset input for INMODE pipeline registers// Data: 30-bit (each) Data Ports.A(A),// 30-bit A data input.B(B),// 18-bit B data input.C(C),// 48-bit C data input.CARRYIN(CARRYIN),// 1-bit carry input signal.D(D),// 25-bit D data input// Reset/Clock Enable: 1-bit (each) Reset/Clock Enable Inputs.CEA1(CEA1),// 1-bit active high clock enable input for 1st stage A registers.CEA2(CEA2),// 1-bit active high clock enable input for 2nd stage A registers.CEAD(CEAD),// 1-bit active high clock enable input for pre-adder output registers.CEALUMODE(CEALUMODE),// 1-bit active high clock enable input for ALUMODE registers.CEB1(CEB1),// 1-bit active high clock enable input for 1st stage B registers.CEB2(CEB2),// 1-bit active high clock enable input for 2nd stage B registers.CEC(CEC),// 1-bit active high clock enable input for C registers.CECARRYIN(CECARRYIN),// 1-bit active high clock enable input for CARRYIN register.CECTRL(CECTRL),// 1-bit active high clock enable input for OPMODE and carry registers.CED(CED),// 1-bit active high clock enable input for D registers.CEM(CEM),// 1-bit active high clock enable input for multiplier registers.CEP(CEP),// 1-bit active high clock enable input for P registers.RSTA(RSTA),// 1-bit reset input for A pipeline registers.RSTALLCARRYIN(RSTALLCARRYIN), // 1-bit reset input for carry pipeline registers.RSTALUMODE(RSTALUMODE),// 1-bit reset input for ALUMODE pipeline registers.RSTB(RSTB),// 1-bit reset input for B pipeline registers.RSTC(RSTC),// 1-bit reset input for C pipeline registers.RSTCTRL(RSTCTRL),// 1-bit reset input for OPMODE pipeline registersVirtex-6 Libraries Guide for HDL Designs128 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design Elements);.RSTD(RSTD),.RSTM(RSTM),.RSTP(RSTP)// 1-bit reset input for D pipeline registers// 1-bit reset input for multiplier registers// 1-bit reset input for P pipeline registers// End of DSP48E1_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 129

Chapter 4: About Design ElementsEFUSE_USRPrimitive: 32-bit non-volatile design IDIntroductionUse this element to internally access 32 non-volatile fuses that can store bits specific to the design (e.g. a uniqueID associated with each design). These efuses must be externally written through JTAG.Port DescriptionsPort Type Width FunctionEFUSEUSR[31:0] Output 32 User E-Fuse register valueDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionSIM_EFUSE_VALUE Hexadecimal 32’h00000000 to32’hffffffff32’h00000000 Causes simulation model to drive astatic value onto these pins after INITgoes high.VHDL Instantiation Template-- EFUSE_USR: 32-bit non-volatile design ID-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2EFUSE_USR_inst : EFUSE_USRgeneric map (SIM_EFUSE_VALUE => X"00000000")port map (EFUSEUSR => EFUSEUSR);-- End of EFUSE_USR_inst instantiation-- Causes simulation model to drive a static value onto these pins after-- INIT goes high.-- 32-bit User E-Fuse register valueVirtex-6 Libraries Guide for HDL Designs130 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// EFUSE_USR: 32-bit non-volatile design ID// Virtex-6// Xilinx HDL Language Template, version 11.1EFUSE_USR #(.SIM_EFUSE_VALUE(32’h00000000))EFUSE_USR_inst (.EFUSEUSR(EFUSEUSR));// End of EFUSE_USR_inst instantiation// Causes simulation model to drive a static value onto these pins after// INIT goes high.// 32-bit User E-Fuse register valueFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 131

Chapter 4: About Design ElementsFDCEPrimitive: D Flip-Flop with Clock Enable and Asynchronous ClearIntroductionThis design element is a single D-type flip-flop with clock enable and asynchronous clear. When clock enable(CE) is High and asynchronous clear (CLR) is Low, the data on the data input (D) of this design element istransferred to the corresponding data output (Q) during the Low-to-High clock (C) transition. When CLR is High,it overrides all other inputs and resets the data output (Q) Low. When CE is Low, clock transitions are ignored.This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.Logic TableInputsOutputsCLR CE D C Q1 X X X 00 0 X X No Change0 1 D ↑ DDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Binary 0 0 Sets the initial value of Q output after configuration.For Spartan®-6 devices, the INIT value shouldalways match the polarity of the set or reset. In thecase of FDCE, the INIT should be 0. If set to 1, anasynchronous circuit must be created to exhibit thisbehavior, which Xilinx does not recommend.Virtex-6 Libraries Guide for HDL Designs132 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and-- Clock Enable (posedge clk). All families.-- Xilinx HDL Libraries Guide, version 11.2FDCE_inst : FDCEgeneric map (INIT => ’0’) -- Initial value of register (’0’ or ’1’)port map (Q => Q, -- Data outputC => C, -- Clock inputCE => CE, -- Clock enable inputCLR => CLR, -- Asynchronous clear inputD => D -- Data input);-- End of FDCE_inst instantiationVerilog Instantiation Template// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and// Clock Enable (posedge clk).// All families.// Xilinx HDL Libraries Guide, version 11.2FDCE #(.INIT(1’b0) // Initial value of register (1’b0 or 1’b1)) FDCE_inst (.Q(Q), // Data output.C(C), // Clock input.CE(CE), // Clock enable input.CLR(CLR), // Asynchronous clear input.D(D) // Data input);// End of FDCE_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 133

Chapter 4: About Design ElementsFDPEPrimitive: D Flip-Flop with Clock Enable and Asynchronous PresetIntroductionThis design element is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset(PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the(Q) output High. Data on the (D) input is loaded into the flip-flop when PRE is Low and CE is High on theLow-to-High clock (C) transition. When CE is Low, the clock transitions are ignored.For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.Logic TableInputsOutputsPRE CE D C Q1 X X X 10 0 X X No Change0 1 D ↑ DDesign Entry MethodThis design element is only for use in schematics.Available AttributesAttribute Type Allowed Values Default DescriptionINIT Binary 1 1 Sets the initial value of Q output after configuration.For Spartan®-6 devices the INIT value should alwaysmatch the polarity of the set or reset. In the case ofFDPE, the init should be 1. If set to 0, an asynchronouscircuit must be created to exhibit this behavior, whichXilinx does not recommend.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs134 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsFDREPrimitive: D Flip-Flop with Clock Enable and Synchronous ResetIntroductionThis design element is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputsand data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q)output Low on the Low-to-High clock (C) transition. The data on the (D) input is loaded into the flip-flop when Ris Low and CE is High during the Low-to-High clock transition.This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.Logic TableInputsOutputsR CE D C Q1 X X ↑ 00 0 X X No Change0 1 D ↑ DDesign Entry MethodThis design element is only for use in schematics.Available AttributesAttribute Type Allowed Values Default DescriptionINIT Binary 0 0 Sets the initial value of Q output after configuration.For Spartan®-6 the INIT value should always matchthe polarity of the set or reset. In the case of FDRE, theINIT should be 0. If set to 1, extra logic is inserted.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 135

Chapter 4: About Design ElementsFDSEPrimitive: D Flip-Flop with Clock Enable and Synchronous SetIntroductionFDSE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output(Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input and sets the Q output Highduring the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when S is Lowand CE is High during the Low-to-High clock (C) transition.For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.Logic TableInputsOutputsS CE D C Q1 X X ↑ 10 0 X X No Change0 1 D ↑ DDesign Entry MethodThis design element is only for use in schematics.Available AttributesAttributeTypeAllowedValues Default DescriptionINIT Binary 1 1 Sets the initial value of Q output after configuration.For Spartan®-6 devices the INIT value should always match thepolarity of the set or reset. In the case of FDSE, the init should be 1.If set to 0, extra logic is inserted.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs136 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsFIFO18E1Primitive: 18 k-bit FIFO (First In, First Out) Block RAM MemoryIntroductionVirtex®-6 devices contain several block RAM memories, each of which can be separately configured as a FIFO, anautomatic error-correction RAM, or as a general-purpose 36 kb or 18 kb RAM/ROM memory. These Block RAMmemories offer fast and flexible storage of large amounts of on-chip data. The FIFO18E1 uses the FIFO controllogic and the 18 kb block RAM. This primitive can be used in a 4-bit wide by 4K deep, 9-bit wide by 2K deep,18-bit wide by 1K deep, or a 36-bit wide by 512 deep configuration. The primitive can be configured in eithersynchronous or dual-clock (asynchronous) mode, with all associated FIFO flags and status signals When usingthe dual-clock mode with independent clocks, depending on the offset between read and write clock edges, theEmpty, Almost Empty, Full and Almost Full flags can deassert one cycle later. Due to the asynchronous nature ofthe clocks the simulation model only reflects the deassertion latency cycles listed in the User GuideNote For a 36-bit wide by 512 deep FIFO, the FIFO18_36 mode must be used. For deeper or wider configurationsof the FIFO, the FIFO36E1 can be used. If error-correction circuitry is desired, the FIFO36E1 with FIFO36_72mode must be used.Port DescriptionsPort Type Width FunctionALMOSTEMPTY Output 1 Programmable flag to indicate the FIFO is almost empty.ALMOST_EMPTY_OFFSET attribute specifies the thresholdwhere this flag is triggered relative to full/empty.ALMOSTFULL Output 1 Programmable flag to indicate that the FIFO is almostfull. The ALMOST_FULL_OFFSET attribute specifies thethreshold where this flag is triggered relative to full/empty.DI[31:0] Input 32 FIFO data input bus.DIP[3:0] Input 4 FIFO parity data input bus.DO[31:0] Output 32 FIFO data output bus.DOP[3:0] Output 4 FIFO parity data output bus.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 137

Chapter 4: About Design ElementsPort Type Width FunctionEMPTY Output 1 Active High logic to indicate that the FIFO is currentlyempty.FULL Output 1 Active High logic indicates that the FIFO is full.RDEN Input 1 Active High FIFO read enable.REGCE Input 1 Output register clock enable for pipelined synchronousFIFO.RST Input 1 Active High (FIFO logic) asynchronous reset (for dual-clockFIFO), synchronous reset (synchronous FIFO) for 3 CLKcycles.RSTREG Input 1 Output register synchronous set/reset.WRCLK,RDCLKWRCOUNT,RDCOUNTInput 1 FIFO read and write clocks (positive edge triggered).Output 12 FIFO write/read pointer.WREN Input 1 Active High FIFO write enable.WRERR,RDERROutput 1 • WRERR indicates that a write occurred while the FIFOwas full.• RDERR indicates that a read occurred while the FIFOwas empty.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedAvailable AttributesAttribute Type Allowed Values Default DescriptionALMOST_EMPTY_OFFSETALMOST_FULL_OFFSETHexadecimalHexadecimal13’h0000 to13’h819113’h0000 to13’h819113’h0080 Specifies the amount of datacontents in the RAM to trigger theALMOST_EMPTY flag.13’h0080 Specifies the amount of datacontents in the RAM to trigger theALMOST_FULL flag.DATA_WIDTH Integer 4, 9, 18, 36 4 Specifies the desired data width forthe FIFO.DO_REG Integer 1, 0 1 Data pipeline register for EN_SYN.EN_SYN Boolean FALSE, TRUE FALSE Specifies whether the FIFO is operatingin either dual-clock (two independentclocks) or synchronous (singleclock) mode. Dual-clock must useDO_REG=1.FIFO_MODE String “FIFO18”,“FIFO18_36”“FIFO18”Selects FIFO18 or FIFO18_36 mode.Virtex-6 Libraries Guide for HDL Designs138 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionFIRST_WORD_FALL_THROUGHINITSRVALBoolean FALSE, TRUE FALSE If TRUE, the first write to the FIFOappears on DO without a first RDENassertion.HexadecimalHexadecimalAny 36 bit Value All zeros Specifies the initial value on the DOoutput after configuration.Any 36 bit Value All zeros Specifies the output value of the FIFOupon assertion of the synchronousreset (RSTREG) signal. Only valid forDO_REG=1.VHDL Instantiation Template-- FIFO18E1: 18KB FIFO (First In, First Out) Block RAM Memory-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2FIFO18E1_inst : FIFO18E1generic map (ALMOST_EMPTY_OFFSET => X"00080", -- Sets the almost empty thresholdALMOST_FULL_OFFSET => X"00080", -- Sets almost full thresholdDATA_WIDTH => 4, -- Sets data width to 4, 9, 18, or 36DO_REG => 1,-- Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE"EN_SYN => FALSE,-- Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE")FIFO_MODE => "FIFO18",-- Sets mode to FIFO18 or FIFO18_36FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to "TRUE" or "FALSE"INIT => X"000000000",-- Initial values on output portSRVAL => X"000000000"-- Set/Reset value for output port)port map (ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit almost empty output flagALMOSTFULL => ALMOSTFULL, -- 1-bit almost full output flagDO => DO,-- 32-bit data outputDOP => DOP,-- 4-bit parity data outputEMPTY => EMPTY,-- 1-bit empty output flagFULL => FULL,-- 1-bit full output flag-- WRCOUNT, RDCOUNT: 12-bit (each) FIFO write/read pointer.RDCOUNT => RDCOUNT,-- 12-bit read count outputWRCOUNT => WRCOUNT,-- 12-bit write count output-- WRERR, RDERR: 1-bit (each) WRERR indicates that a write occurred while the FIFO was full and RDERR-- indicates that a read occurred while the FIFO was emptyRDERR => RDERR,-- 1-bit read error outputWRERR => WRERR,-- 1-bit write errorDI => DI,-- 32-bit data inputDIP => DIP,-- 4-bit parity inputRDEN => RDEN,-- 1-bit read enable inputREGCE => REGCE,-- 1-bit clock enable inputRST => RST,-- 1-bit reset inputRSTREG => RSTREG,-- 1-bit output register set/reset-- WRCLK, RDCLK: 1-bit (each) FIFO read and write clocks (positive edgetriggered).RDCLK => RDCLK,-- 1-bit read clock inputWRCLK => WRCLK,-- 1-bit write clock inputWREN => WREN-- 1-bit write enable input);-- End of FIFO18E1_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 139

Chapter 4: About Design ElementsVerilog Instantiation Template// FIFO18E1: 18KB FIFO (First In, First Out) Block RAM Memory// Virtex-6// Xilinx HDL Language Template, version 11.1FIFO18E1 #(.ALMOST_EMPTY_OFFSET(13’h0080), // Sets the almost empty threshold.ALMOST_FULL_OFFSET(13’h0080), // Sets almost full threshold.DATA_WIDTH(4), // Sets data width to 4, 9, 18, or 36.DO_REG(1),// Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE".EN_SYN("FALSE"),// Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE").FIFO_MODE("FIFO18"),// Sets mode to FIFO18 or FIFO18_36.FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to "TRUE" or "FALSE".INIT(36’h000000000),// Initial values on output port.SRVAL(36’h000000000)// Set/Reset value for output port)FIFO18E1_inst (.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag.DO(DO),// 32-bit data output.DOP(DOP),// 4-bit parity data output.EMPTY(EMPTY),// 1-bit empty output flag.FULL(FULL),// 1-bit full output flag// WRCOUNT, RDCOUNT: 12-bit (each) FIFO write/read pointer..RDCOUNT(RDCOUNT),// 12-bit read count output.WRCOUNT(WRCOUNT),// 12-bit write count output// WRERR, RDERR: 1-bit (each) WRERR indicates that a write occurred while the FIFO was full and RDERR// indicates that a read occurred while the FIFO was empty.RDERR(RDERR),// 1-bit read error output.WRERR(WRERR),// 1-bit write error.DI(DI),// 32-bit data input.DIP(DIP),// 4-bit parity input.RDEN(RDEN),// 1-bit read enable input.REGCE(REGCE),// 1-bit clock enable input.RST(RST),// 1-bit reset input.RSTREG(RSTREG),// 1-bit output register set/reset// WRCLK, RDCLK: 1-bit (each) FIFO read and write clocks (positive edgeggered)..RDCLK(RDCLK),// 1-bit read clock input.WRCLK(WRCLK),// 1-bit write clock input.WREN(WREN)// 1-bit write enable input);// End of FIFO18E1_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs140 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsFIFO36E1Primitive: 36 kb FIFO (First In, First Out) Block RAM MemoryIntroductionVirtex®-6 devices contain several block RAM memories that can be configured as FIFOs, automaticerror-correction RAM, or general-purpose 36 kb or 18 kb RAM/ROM memories. These block RAM memoriesoffer fast and flexible storage of large amounts of on-chip data. The FIFO36E1 allows access to the block RAM inthe 36 kb FIFO configurations. This component can be configured and used as a 4-bit wide by 8K deep, 9-bitby 4K deep, 18-bit by 2K deep, 36-bit wide by 1K deep, or 72-bit wide by 512 deep synchronous or dual-clock(asynchronous) FIFO RAM with all associated FIFO flags.When using the dual-clock mode with independent clocks, depending on the offset between read and write clockedges, the Empty, Almost Empty, Full, and Almost Full flags can deassert one cycle later. Due to the asynchronousnature of the clocks, the simulation model only reflects the deassertion latency cycles listed in the User Guide.Note For a 72-bit wide by 512 deep FIFO, the FIFO36_72 mode must be used. For smaller configurations of theFIFO, the FIFO18E1 can be used. If error-correction circuitry is desired, the FIFO36_72 mode must be used.Port DescriptionsPort Type Width FunctionALMOSTEMPTY Output 1 Programmable flag to indicate the FIFO is almost empty.ALMOST_EMPTY_OFFSET attribute specifies where totrigger this flag.ALMOSTFULL Output 1 Programmable flag to indicate the FIFO is almost full.ALMOST_FULL_OFFSET attribute specifies where totrigger this flag.DBITERR Output 1 Status output from ECC function to indicate a double biterror was detected. EN_ECC_READ needs to be TRUE inorder to use this functionality.DI[63:0] Input 64 FIFO data input bus.DIP[7:0] Input 8 FIFO parity data input bus.DO[63:0] Output 64 FIFO data output bus.DOP[7:0] Output 8 FIFO parity data output bus.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 141

Chapter 4: About Design ElementsPort Type Width FunctionECCPARITY[7:0] Output 8 8-bit data generated by the ECC encoder used by the ECCdecoder for memory error detection and correction.EMPTY Output 1 Active high logic to indicate that the FIFO is currentlyempty.FULL Output 1 Active high logic indicates that the FIFO is full.INJECTDBITERR Input 1 Inject a double bit error if ECC feature is used.INJECTSBITERR Input 1 Inject a single bit error if ECC feature is used.RDEN Input 1 Active high FIFO read enable.REGCE Input 1 Output register clock enable for pipelined synchronousFIFO.RST Input 1 Active high (FIFO logic) asynchronous reset (for dual-clockFIFO), synchronous reset (synchronous FIFO) for 3 CLKcycles.RSTREG Input 1 Output register synchronous set/reset.SBITERR Output 1 Status output from ECC function to indicate a single biterror was detected. EN_ECC_READ needs to be TRUE inorder to use this functionality.WRCLK, RDCLK Input 1 FIFO read and write clocks (positive edge triggered).WRCOUNT,RDCOUNTOutput 13 FIFO write/read pointer.WREN Input 1 Active high FIFO write enable.WRERR,RDERROutput 1 • WRERR indicates that a write occurred while the FIFOwas full.• RDERR indicates that a read occurred while the FIFOwas empty.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedAvailable AttributesAttribute Type Allowed Values Default DescriptionALMOST_EMPTY_OFFSETALMOST_FULL_OFFSETHexadecimalHexadecimal13’h0000 to 13’h8191 13’h0080 Specifies the amount of datacontents in the RAM to trigger theALMOST_EMPTY flag.13’h0000 to 13’h8191 13’h0080 Specifies the amount of datacontents in the RAM to trigger theALMOST_FULL flag.DATA_WIDTH Integer 4, 9, 18, 36, 72 4 Specifies the desired data width forthe FIFO.DO_REG Integer 1, 0 1 Enable output register to the FIFO forimproved clock-to-out timing at theexpense of added read latency (oneVirtex-6 Libraries Guide for HDL Designs142 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsAttribute Type Allowed Values Default Descriptionpipeline delay). DO_REG must be 1when EN_SYN is set to FALSE.EN_ECC_READ Boolean FALSE, TRUE FALSE Enable the ECC decoder circuitry.EN_ECC_WRITE Boolean FALSE, TRUE FALSE Enable the ECC encoder circuitry.EN_SYN Boolean FALSE, TRUE FALSE When FALSE, specifies the FIFO tobe used in asynchronous mode (twoindependent clock). When TRUE insynchronous (a single clock) operation.FIFO_MODE String “FIFO36”,“FIFO36_72”FIRST_WORD_FALL_THROUGHINITSRVAL“FIFO36”Selects FIFO36 or FIFO36_72 mode.Boolean FALSE, TRUE FALSE If TRUE, the first write to the FIFOwill appear on DO without an RDENassertion.HexadecimalHexadecimalAny 72 bit Value All zeros Specifies the initial value on the DOoutput after configuration.Any 72 bit Value All zeros Specifies the output value of the FIFOupon assertion of the synchronousreset (RSTREG) signal. Only valid forDO_REG=1.VHDL Instantiation Template-- FIFO36E1: 36KB FIFO (First In, First Out) Block RAM Memory-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2FIFO36E1_inst : FIFO36E1generic map (ALMOST_EMPTY_OFFSET => X"00080", -- Sets the almost empty thresholdALMOST_FULL_OFFSET => X"00080", -- Sets almost full thresholdDATA_WIDTH => 4, -- Sets data width to 4, 9, 18, 36, or 72DO_REG => 1,-- Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE"EN_ECC_READ => FALSE,-- Enable ECC decoder, "TRUE" or "FALSE"EN_ECC_WRITE => FALSE,-- Enable ECC encoder, "TRUE" or "FALSE"EN_SYN => FALSE,-- Specifies FIFO as Asynchronous ("FALSE") or Synchronous ("TRUE")FIFO_MODE => "FIFO36",-- Sets mode to FIFO36 or FIFO36_72FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to "TRUE" or "FALSE"INIT => X"000000000000000000", -- Initial values on output portSRVAL => X"000000000000000000"-- Set/Reset value for output port)port map (ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit almost empty output flagALMOSTFULL => ALMOSTFULL, -- 1-bit almost full output flagDBITERR => DBITERR,-- 1-bit double bit error status outputDO => DO,-- 64-bit data outputDOP => DOP,-- 8-bit parity data outputECCPARITY => ECCPARITY,-- 8-bit generated error correction parityEMPTY => EMPTY,-- 1-bit empty output flagFULL => FULL,-- 1-bit full output flagSBITERR => SBITERR,-- 1-bit single bit error status output-- WRCOUNT, RDCOUNT: 13-bit (each) FIFO write/read pointer.RDCOUNT => RDCOUNT,-- 9-bit read count outputWRCOUNT => WRCOUNT,-- 9-bit write count output-- WRERR, RDERR: 1-bit (each) WRERR indicates that a write occurred while the FIFO was full and RDERR-- indicates that a read occurred while the FIFO was emptyRDERR => RDERR,-- 1-bit read error outputWRERR => WRERR,-- 1-bit write errorDI => DI,-- 64-bit data inputDIP => DIP,-- 8-bit parity inputINJECTDBITERR => INJECTDBITERR, -- 1-bit Inject a double bit error if ECC feature is used.INJECTSBITERR => INJECTSBITERR, -- 1-bit Inject a single bit error if ECC feature is used.RDEN => RDEN,-- 1-bit read enable inputREGCE => REGCE,-- 1-bit clock enable inputVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 143

Chapter 4: About Design ElementsRST => RST,-- 1-bit reset inputRSTREG => RSTREG,-- 1-bit output register set/reset-- WRCLK, RDCLK: 1-bit (each) FIFO read and write clocks (positive edgetriggered).RDCLK => RDCLK,-- 1-bit read clock inputWRCLK => WRCLK,-- 1-bit write clock inputWREN => WREN-- 1-bit write enable input);-- End of FIFO36E1_inst instantiationVerilog Instantiation Template// FIFO36E1: 36KB FIFO (First In, First Out) Block RAM Memory// Virtex-6// Xilinx HDL Language Template, version 11.1FIFO36E1 #(.ALMOST_EMPTY_OFFSET(13’h0080), // Sets the almost empty threshold.ALMOST_FULL_OFFSET(13’h0080), // Sets almost full threshold.DATA_WIDTH(4), // Sets data width to 4, 9, 18, 36, or 72.DO_REG(1),// Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE".EN_ECC_READ("FALSE"),// Enable ECC decoder, "TRUE" or "FALSE".EN_ECC_WRITE("FALSE"),// Enable ECC encoder, "TRUE" or "FALSE".EN_SYN("FALSE"),// Specifies FIFO as Asynchronous ("FALSE") or Synchronous ("TRUE").FIFO_MODE("FIFO36"),// Sets mode to FIFO36 or FIFO36_72.FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to "TRUE" or "FALSE".INIT(72’h000000000000000000), // Initial values on output port.SRVAL(72’h000000000000000000) // Set/Reset value for output port)FIFO36E1_inst (.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag.DBITERR(DBITERR),// 1-bit double bit error status output.DO(DO),// 64-bit data output.DOP(DOP),// 8-bit parity data output.ECCPARITY(ECCPARITY),// 8-bit generated error correction parity.EMPTY(EMPTY),// 1-bit empty output flag.FULL(FULL),// 1-bit full output flag.SBITERR(SBITERR),// 1-bit single bit error status output// WRCOUNT, RDCOUNT: 13-bit (each) FIFO write/read pointer..RDCOUNT(RDCOUNT),// 9-bit read count output.WRCOUNT(WRCOUNT),// 9-bit write count output// WRERR, RDERR: 1-bit (each) WRERR indicates that a write occurred while the FIFO was full and RDERR// indicates that a read occurred while the FIFO was empty.RDERR(RDERR),// 1-bit read error output.WRERR(WRERR),// 1-bit write error.DI(DI),// 64-bit data input.DIP(DIP),// 8-bit parity input.INJECTDBITERR(INJECTDBITERR), // 1-bit Inject a double bit error if ECC feature is used..INJECTSBITERR(INJECTSBITERR), // 1-bit Inject a single bit error if ECC feature is used..RDEN(RDEN),// 1-bit read enable input.REGCE(REGCE),// 1-bit clock enable input.RST(RST),// 1-bit reset input.RSTREG(RSTREG),// 1-bit output register set/reset// WRCLK, RDCLK: 1-bit (each) FIFO read and write clocks (positive edgeggered)..RDCLK(RDCLK),// 1-bit read clock input.WRCLK(WRCLK),// 1-bit write clock input.WREN(WREN)// 1-bit write enable input);// End of FIFO36E1_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs144 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsFRAME_ECC_VIRTEX6Primitive: Virtex®-6 Configuration Frame Error Detection and Correction CircuitryIntroductionThis design element enables the dedicated, built-in ECC (Error Detection and Correction Circuitry) for theconfiguration memory of the FPGA. This element contains outputs that allow monitoring of the status of the ECCcircuitry and the status of the readback CRC circuitry.SEU Correction feature provides hardware version to allow automatic correction of single-bit errors. Newadditional outputs used by the correction feature include the decoding of the Hamming code syndromefor use by the soft core.Port DescriptionsPort Type Width FunctionCRCERROR Output 1 Readback CRC error.ECCERROR Output 1 Frame ECC error found. Value is a one when SYNDROME isnon-zero and a zero when SYNDROME is all zeroes indicatingno errors detected.ECCERRORSINGLE Output 1 Indicates single-bit Frame ECC error detected.FAR[23:0] Output 24 SEU Correction/Injection and ICAP applications can benefit frombeing able to see the FAR register This output can point to the EFARor FAR configuration register depending on the FARSRC attribute.SYNBIT[4:0] Output 5 The index (0 -> 31) of the bit w/ error in the word pointed to bySYNWORD in the frame detected. Valid when ECCERRORSINGLEis high.SYNDROME[12:0] Output 13 Frame ECC error where:• S[12] = 0, S[11:0] = 0: no error.• S[12] = 1, S[11:0] ≠ 0: single bit (SED) error; S[11:0] denoteslocation of error.• S[12] = 1, S[11:0] = 0: single-bit error; overall parity bit p[11]is in error.• S[12] = 0, S[11:0] ≠ 0: double-bit error, not correctable.SYNDROMEVALID Output 1 Frame ECC output indicating that the value on SYNDROME isvalid.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 145

Chapter 4: About Design ElementsPort Type Width FunctionSYNWORD[6:0] Output 7 The index (0 -> 80) of the 32-bit word in the frame where an ECCerror has been detected. Decoded from SYNDROME. Valid whenECCERRORSINGLE is high.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed_Values Default DescriptionFARSRC String “EFAR”, “FAR” “EFAR” Determines if the output of FAR[23:0] is pointed tothe FAR or EFAR configuration register. Sets configoption register bit CTL0[7].VHDL Instantiation Template-- FRAME_ECC_VIRTEX6: Virtex-6 Configuration Frame Error Detection and Correction Circuitry-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2FRAME_ECC_VIRTEX6_inst : FRAME_ECC_VIRTEX6generic map (FARSRC => "EFAR")port map (CRCERROR => CRCERROR,ECCERROR => ECCERROR,-- Determines if the output of FAR[23:0] is pointed to the FAR or EFAR configuration-- register. Sets config option register bit REG_TBD[bit].-- 1-bit Readback CRC error.-- 1-bit Frame ECC error found. Value is a one when SYNDROME is-- non-zero and a zero when SYNDROME is all zeroes indicating no errors-- detected.ECCERRORSINGLE => ECCERRORSINGLE, -- 1-bit Indicates single-bit Frame ECC error detected.FAR => FAR,-- 24-bit SEU Correction/Injection and ICAP applications can benefit-- from being able to see the FAR register This output can point to the-- EFAR or FAR configuration register depending on the FARSRC-- attribute.SYNBIT => SYNBIT,SYNDROME => SYNDROME,SYNDROMEVALID => SYNDROMEVALID,SYNWORD => SYNWORD-- 5-bit The index (0 -> 31) of the bit w/ error in the word pointed to-- by SYNWORD in the frame detected. Valid when ECCERRORSINGLE is high.-- 13-bit Frame ECC error where: No errors: All zeros One bit error:-- SYNDROME[11]=0, SYNDROME[10:0]= location of error in FRAME Two bit-- errors: SYNDROME[11]=1, SYNDROME[10:0]=dont care More than two bit-- errors: Unknown output.-- 1-bit Frame ECC output indicating that the value on SYNDROME is-- valid.-- 7-bit The index (0 -> 80) of the 32-bit word in the frame where an-- ECC error has been detected. Decoded from SYNDROME. Valid when-- ECCERRORSINGLE is high.);-- End of FRAME_ECC_VIRTEX6_inst instantiationVirtex-6 Libraries Guide for HDL Designs146 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// FRAME_ECC_VIRTEX6: Virtex-6 Configuration Frame Error Detection and Correction Circuitry// Virtex-6// Xilinx HDL Language Template, version 11.1FRAME_ECC_VIRTEX6 #(.FARSRC("EFAR"))FRAME_ECC_VIRTEX6_inst (.CRCERROR(CRCERROR),.ECCERROR(ECCERROR),// Determines if the output of FAR[23:0] is pointed to the FAR or EFAR configuration// register. Sets config option register bit REG_TBD[bit].// 1-bit Readback CRC error.// 1-bit Frame ECC error found. Value is a one when SYNDROME is non-zero// and a zero when SYNDROME is all zeroes indicating no errors detected..ECCERRORSINGLE(ECCERRORSINGLE), // 1-bit Indicates single-bit Frame ECC error detected..FAR(FAR),// 24-bit SEU Correction/Injection and ICAP applications can benefit// from being able to see the FAR register This output can point to the// EFAR or FAR configuration register depending on the FARSRC attribute..SYNBIT(SYNBIT),.SYNDROME(SYNDROME),.SYNDROMEVALID(SYNDROMEVALID),.SYNWORD(SYNWORD)// 5-bit The index (0 -> 31) of the bit w/ error in the word pointed to// by SYNWORD in the frame detected. Valid when ECCERRORSINGLE is high.// 13-bit Frame ECC error where: No errors: All zeros One bit error:// SYNDROME[11]=0, SYNDROME[10:0]= location of error in FRAME Two bit// errors: SYNDROME[11]=1, SYNDROME[10:0]=dont care More than two bit// errors: Unknown output.// 1-bit Frame ECC output indicating that the value on SYNDROME is valid.// 7-bit The index (0 -> 80) of the 32-bit word in the frame where an// ECC error has been detected. Decoded from SYNDROME. Valid when// ECCERRORSINGLE is high.);// End of FRAME_ECC_VIRTEX6_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 147

Chapter 4: About Design ElementsGTHE1_QUADPrimitive: Gigabit TransceiverVirtex-6 Libraries Guide for HDL Designs148 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsIntroductionThis design element represents the Virtex®-6 FPGA GTH transceiver. GTH is the highest performance,10G-optimized configurable transceiver in the Virtex-6 FPGA as part of the HXT family. Refer to Virtex-6 FPGAGTH Transceivers User Guide for detailed information regarding this component. The Virtex-6 FPGA GTHTransceivers Wizard is the preferred tool to generate a wrapper to instantiate a GTHE1_QUAD primitive. TheWizard can be found in the Xilinx® CORE Generator tool.Design Entry MethodTo instantiate this component, use the Virtex-6 FPGA GTH Transceivers Wizard or an associated core containingthe component. Xilinx does not recommend direct instantiation of this component.For More Information• See the Virtex-6 FPGA GTH Transceivers User Guide.• See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 149

Chapter 4: About Design ElementsGTXE1Primitive: Gigabit TransceiverIntroductionThis design element represents the Virtex®-6 FPGA RocketIO GTX transceiver, a power-efficient and highlyconfigurable transceiver. Refer to Virtex-6 FPGA RocketIO GTX Transceiver User Guide for detailed informationregarding this component. The Virtex-6 FPGA RocketIO GTX Transceiver Wizard is the preferred tool to generatea wrapper to instantiate a GTXE1 primitive. The Wizard can be found in the Xilinx® CORE Generator tool.Virtex-6 Libraries Guide for HDL Designs150 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsDesign Entry MethodTo instantiate this component, use the Virtex-6 FPGA RocketIO GTX Transceiver Wizard or an associated corecontaining the component. Xilinx does not recommend direct instantiation of this component.For More Information• See the Virtex-6 FPGA RocketIO GTX Transceivers User Guide.• See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 151

Chapter 4: About Design ElementsIBUFPrimitive: Input BufferIntroductionThis design element is automatically inserted (inferred) by the synthesis tool to any signal directly connectedto a top-level input or in-out port of the design. You should generally let the synthesis tool infer this buffer.However, it can be instantiated into the design if required. In order to do so, connect the input port (I) directly tothe associated top-level input or in-out port, and connect the output port (O) to the logic sourced by that port.Modify any necessary generic maps (VHDL) or named parameter value assignment (Verilog) in order to changethe default behavior of the component.Port DescriptionsPort Direction Width FunctionO Output 1 Buffer outputI Input 1 Buffer inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoIn general, this element is inferred by the synthesis tool for any specified top-level input port to the design. It isgenerally not necessary to specify them in the source code. However, if desired, they be manually instantiated byeither copying the instantiation code from the appropriate Libraries Guide HDL template and pasting it into thetop-level entity/module of your code. It is recommended to always put all I/O components on the top-level of thedesign to help facilitate hierarchical design methods. Connect the I port directly to the top-level input port of thedesign and the O port to the logic in which this input is to source. Specify the desired generic/defparam values inorder to configure the proper behavior of the buffer.Available AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet. "DEFAULT" Assigns an I/O standard to the element.Virtex-6 Libraries Guide for HDL Designs152 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IBUF: Single-ended Input Buffer-- All devices-- Xilinx HDL Libraries Guide, version 11.2IBUF_inst : IBUFgeneric map (IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,-- "0"-"12" (Spartan-3E)-- "0"-"16" (Spartan-3A)IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register,-- "AUTO", "0"-"6" (Spartan-3E)-- "AUTO", "0"-"8" (Spartan-3A)IOSTANDARD => "DEFAULT")port map (O => O, -- Buffer outputI => I -- Buffer input (connect directly to top-level port));-- End of IBUF_inst instantiationVerilog Instantiation Template// IBUF: Single-ended Input Buffer// All devices// Xilinx HDL Libraries Guide, version 11.2IBUF #(.IBUF_DELAY_VALUE("0"),// Specify the amount of added input delay for// the buffer: "0"-"12" (Spartan-3E)// "0"-"16" (Spartan-3A).IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input// register: "AUTO", "0"-"6" (Spartan-3E)// "AUTO", "0"-"8" (Spartan-3A).IOSTANDARD("DEFAULT") // Specify the input I/O standard)IBUF_inst (.O(O), // Buffer output.I(I) // Buffer input (connect directly to top-level port));// End of IBUF_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 153

Chapter 4: About Design ElementsIBUFDSPrimitive: Differential Signaling Input BufferIntroductionThis design element is an input buffer that supports low-voltage, differential signaling. In IBUFDS, a designlevel interface signal is represented as two distinct ports (I and IB), one deemed the "master" and the other the"slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET_P andMYNET_N). Optionally, a programmable differential termination feature is available to help improve signalintegrity and reduce external components.Logic TableInputsI IB OOutputs0 0 No Change0 1 01 0 11 1 No ChangePort DescriptionsPort Type Width FunctionI Input 1 Diff_p Buffer InputIB Input 1 Diff_n Buffer InputO Output 1 Buffer OutputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoPut all I/O components on the top-level of the design to help facilitate hierarchical design methods. Connectthe I port directly to the top-level "master" input port of the design, the IB port to the top-level "slave" inputport, and the O port to the logic in which this input is to source. Specify the desired generic/defparam values inorder to configure the proper behavior of the buffer.Available AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet. "DEFAULT" Assigns an I/O standard to the element.Virtex-6 Libraries Guide for HDL Designs154 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IBUFDS: Differential Input Buffer-- Spartan-3/3E/3A-- Xilinx HDL Libraries Guide, version 11.2IBUFDS_inst : IBUFDSgeneric map (CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only)DIFF_TERM => FALSE, -- Differential Termination (Virtex-4/5, Spartan-3E/3A)IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,-- "0"-"12" (Spartan-3E)-- "0"-"16" (Spartan-3A)IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register,-- "AUTO", "0"-"6" (Spartan-3E)-- "AUTO", "0"-"8" (Spartan-3A)IOSTANDARD => "DEFAULT")port map (O => O, -- Clock buffer outputI => I, -- Diff_p clock buffer input (connect directly to top-level port)IB => IB -- Diff_n clock buffer input (connect directly to top-level port));-- End of IBUFDS_inst instantiationVerilog Instantiation Template// IBUFDS: Differential Input Buffer// Virtex-4/5, Spartan-3/3E/3A// Xilinx HDL Libraries Guide, version 11.2IBUFDS #(.CAPACITANCE("DONT_CARE"), // "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only).DIFF_TERM("FALSE"), // Differential Termination (Virtex-4/5, Spartan-3E/3A).IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for// the buffer: "0"-"12" (Spartan-3E)// "0"-"16" (Spartan-3A).IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input// register: "AUTO", "0"-"6" (Spartan-3E)// "AUTO", "0"-"8" (Spartan-3A).IOSTANDARD("DEFAULT") // Specify the input I/O standard) IBUFDS_inst (.O(O), // Buffer output.I(I), // Diff_p buffer input (connect directly to top-level port).IB(IB) // Diff_n buffer input (connect directly to top-level port));// End of IBUFDS_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 155

Chapter 4: About Design ElementsIBUFDS_GTHE1Primitive: Differential Clock Input for the GTH Transceiver Reference ClocksIntroductionThis component is the dedicated differential clock input for the GTH transceiver reference clocks. There is oneIBUFGDS_GTHE1 component per GTH quad and it connects directly to the REFCLK pin of the GTHE1_QUADprimitive.Design Entry MethodTo instantiate this component, use the Virtex-6 FPGA GTH Transceivers Wizard or an associated core containingthe component. Xilinx does not recommend direct instantiation of this component.For More Information• See the Virtex-6 FPGA GTH Transceivers User Guide.• See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs156 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsIBUFDS_GTXE1Primitive: Differential Clock Input for the Transceiver Reference ClocksIntroductionThis component is the differential clock input for the transceiver reference clocks. It can also drive otherclock resources such as BUFG/MMCM as well as the reference clock inputs of the GT. It typically connectsto the MGTREFCLKRX/TX pins of the 4 GTXE1 in the quad associated with the IBUFDS_GTXE1, to theNORTHREFCLKRX/TX of the 4 GTXE1 in the quad above, or to the SOUTHREFCLKRX/TX pins of the 4 GTXE1in the quad below.There are multiple destination pins in Virtex®-6 devices that the IBUFDS_GTXE1 element could connect to. Ifone reference clock on the GT is connected, SW has full control and can route and connect to the GT on any of thepins based on the most optimal route. If multiple clocks are connected to the GT then SW will route each IBUFDSto the indicated pin on the GT. So the O pin on the IBUFDS_GTXE1 connects to either the MGTREFCLKRX/TX orthe NORTH/SOUTHREFCLKRX/TX pins on the GT.Note The RX and TX MUXes can be chosen independently, but the routes are shared on physical silicon.Design Entry MethodTo instantiate this component, use the RocketIO wizard or an associated core containing the component. Xilinxdoes not recommend direct instantiation of this component.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 157

Chapter 4: About Design ElementsIBUFGPrimitive: Dedicated Input Clock BufferIntroductionThe IBUFG is a dedicated input to the device which should be used to connect incoming clocks to the FPGA’sglobal clock routing resources. The IBUFG provides dedicated connections from a top level port to the MMCMor BUFG providing the minimum amount of clock delay and jitter to the device. The IBUFG input can only bedriven by the clock capable (CC) or global clock (GC) pins.Port DescriptionsPort Direction Width FunctionO Output 1 Clock Buffer outputI Input 1 Clock Buffer inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to theelement.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IBUFG: Global Clock Buffer (sourced by an external pin)-- Xilinx HDL Libraries Guide, version 11.2IBUFG_inst : IBUFGgeneric map (IOSTANDARD => "DEFAULT")port map (O => O, -- Clock buffer outputI => I -- Clock buffer input (connect directly to top-level port));-- End of IBUFG_inst instantiationVirtex-6 Libraries Guide for HDL Designs158 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// IBUFG: Global Clock Buffer (sourced by an external pin)// All FPGAs// Xilinx HDL Libraries Guide, version 11.2IBUFG #(.IOSTANDARD("DEFAULT"),.IBUF_DELAY_VALUE("0")// Specify the amount of added input delay for// the buffer: "0"-"12" (Spartan-3E)// "0"-"16" (Spartan-3A)) IBUFG_inst (.O(O), // Clock buffer output.I(I) // Clock buffer input (connect directly to top-level port));// End of IBUFG_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 159

Chapter 4: About Design ElementsIBUFGDSPrimitive: Differential Signaling Dedicated Input Clock Buffer and Optional DelayIntroductionThis design element is a dedicated differential signaling input buffer for connection to the clock buffer (BUFG) orMMCM. In IBUFGDS, a design-level interface signal is represented as two distinct ports (I and IB), one deemedthe "master" and the other the "slave." The master and the slave are opposite phases of the same logical signal (forexample, MYNET_P and MYNET_N). Optionally, a programmable differential termination feature is available tohelp improve signal integrity and reduce external components. Also available is a programmable delay is toassist in the capturing of incoming data to the device.Logic TableInputsOutputsI IB O0 0 No Change0 1 01 0 11 1 No ChangePort DescriptionsPort Direction Width FunctionO Output 1 Clock Buffer outputIB Input 1 Diff_n Clock Buffer InputI Input 1 Diff_p Clock Buffer InputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoPut all I/O components on the top-level of the design to help facilitate hierarchical design methods. Connect the Iport directly to the top-level "master" input port of the design, the IB port to the top-level "slave" input port andthe O port to an MMCM, BUFG or logic in which this input is to source. Some synthesis tools infer the BUFGautomatically if necessary, when connecting an IBUFG to the clock resources of the FPGA. Specify the desiredgeneric/defparam values in order to configure the proper behavior of the buffer.Virtex-6 Libraries Guide for HDL Designs160 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to theelement.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)-- Virtex-4/5, Spartan-3/3E/3A-- Xilinx HDL Libraries Guide, version 11.2IBUFGDS_inst : IBUFGDSgeneric map (IOSTANDARD => "DEFAULT")port map (O => O, -- Clock buffer outputI => I, -- Diff_p clock buffer inputIB => IB -- Diff_n clock buffer input);-- End of IBUFGDS_inst instantiationVerilog Instantiation Template// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)// Virtex-4/5, Spartan-3/3E/3A// Xilinx HDL Libraries Guide, version 11.2IBUFGDS #(.DIFF_TERM("FALSE"), // Differential Termination (Virtex-4/5, Spartan-3E/3A).IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer.IBUF_DELAY_VALUE("0") // Specify the amount of added input delay for// the buffer: "0"-"12" (Spartan-3E)// "0"-"16" (Spartan-3A)) IBUFGDS_inst (.O(O), // Clock buffer output.I(I), // Diff_p clock buffer input.IB(IB) // Diff_n clock buffer input);// End of IBUFGDS_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 161

Chapter 4: About Design ElementsICAP_VIRTEX6Primitive: Internal Configuration Access PortIntroductionThis design element gives you access to the configuration functions of the FPGA from the FPGA fabric. Usingthis component, commands and data can be written to and read from the configuration logic of the FPGA array.Since the improper use of this function can have a negative effect on the functionality and reliability of the FPGA,you should not use this element unless you are very familiar with its capabilities.Port DescriptionsPort Type Width FunctionBUSY Output 1 Busy/Ready output.CLK Input 1 Clock Input.CSB Input 1 Active-Low ICAP Enable.I[31:0] Input 32 Configuration data input bus.O[31:0] Output 32 Configuration data output bus.RDWRB Input 1 Read/Write Select.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionICAP_WIDTH String “X8”, “X16”,“X32”“X8”Specifies the input and output data widthto be used with the ICAP_VIRTEX6.Virtex-6 Libraries Guide for HDL Designs162 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVHDL Instantiation Template-- ICAP_VIRTEX6: Internal Configuration Access Port-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2ICAP_VIRTEX6_inst : ICAP_VIRTEX6generic map (ICAP_AUTO_SWITCH => "DISABLE",ICAP_WIDTH => "X8")port map (BUSY => BUSY,O => O,CLK => CLK,CSB => CSB,I => I,RDWRB => RDWRB);-- Specifies the input and output data width to be used with the-- ICAP_VIRTEX6.-- 1-bit Busy/Ready output-- 32-bit Configuration data output bus-- 1-bit Clock Input-- 1-bit Active-Low ICAP Enable-- 32-bit Configuration data input bus-- 1-bit Read/Write Select-- End of ICAP_VIRTEX6_inst instantiationVerilog Instantiation Template// ICAP_VIRTEX6: Internal Configuration Access Port// Virtex-6// Xilinx HDL Language Template, version 11.1ICAP_VIRTEX6 #(.ICAP_AUTO_SWITCH("DISABLE"),.ICAP_WIDTH("X8"))ICAP_VIRTEX6_inst (.BUSY(BUSY), // 1-bit Busy/Ready output.O(O),// 32-bit Configuration data output bus.CLK(CLK), // 1-bit Clock Input.CSB(CSB), // 1-bit Active-Low ICAP Enable.I(I),// 32-bit Configuration data input bus.RDWRB(RDWRB) // 1-bit Read/Write Select);// End of ICAP_VIRTEX6_inst instantiation// Specifies the input and output data width to be used with the// ICAP_VIRTEX6.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 163

Chapter 4: About Design ElementsIDDRPrimitive: Input Dual Data-Rate RegisterIntroductionThis design element is a dedicated input register designed to receive external dual data rate (DDR) signals intoXilinx® FPGAs.The IDDR is available with modes that present the data to the FPGA fabric at the time andclock edge they are captured, or on the same clock edge. This feature allows you to avoid additional timingcomplexities and resource usage.• OPPOSITE_EDGE mode - Data is recovered in the classic DDR methodology. Given a DDR data andclock at pin D and C respectively, Q1 changes after every positive edge of clock C, and Q2 changes afterevery negative edge of clock C.• SAME_EDGE mode - Data is still recovered by opposite edges of clock C. However, an extra register has beenplaced in front of the negative edge data register. This extra register is clocked with positive clock edge ofclock signal C. As a result, DDR data is now presented into the FPGA fabric at the same clock edge. However,because of this feature, the data pair appears to be "separated." Q1 and Q2 no longer have pair 1 and 2.Instead, the first pair presented is Pair 1 and DONT_CARE, followed by Pair 2 and 3 at the next clock cycle.• SAME_EDGE_PIPELINED mode - Recovers data in a similar fashion as the SAME_EDGE mode. In orderto avoid the "separated" effect of the SAME_EDGE mode, an extra register has been placed in front of thepositive edge data register. A data pair now appears at the Q1 and Q2 pin at the same time. However, usingthis mode costs you an additional cycle of latency for Q1 and Q2 signals to change.IDDR also works with the SelectIO features, such as the IODELAY.Note For high speed interfaces, the IDDR_2CLK component can be used to specify two independent clocksto capture the data. Use this component when the performance requirements of the IDDR are not adequate,since the IDDR_2CLK requires more clocking resources and can imply placement restrictions that are notnecessary when using the IDDR component.Port DescriptionsPort Direction Width FunctionQ1 - Q2 Output 1 These pins are the IDDR output that connects to the FPGA fabric. Q1 isthe first data pair and Q2 is the second data pair.C Input 1 Clock input pin.CE Input 1 When asserted Low, this port disables the output clock at port O.D Input 1 This pin is where the DDR data is presented into the IDDR module.This pin connects to a top-level input or bi-directional port, andIODELAY configured for an input delay or to an appropriate input orbidirectional buffer.R Input 1 Active high reset forcing Q1 and Q2 to a logic zero. Can be synchronousor asynchronous based on the SRTYPE attribute.S Input 1 Active high reset forcing Q1 and Q2 to a logic one. Can be synchronousor asynchronous based on the SRTYPE attribute.Virtex-6 Libraries Guide for HDL Designs164 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionDDR_CLK_EDGE String "OPPOSITE_EDGE","SAME_EDGE","SAME_EDGE_PIPELINED""OPPOSITE_EDGE”Sets the IDDR mode of operation withrespect to clock edge.INIT_Q1 Binary 0, 1 0 Initial value on the Q1 pin afterconfiguration startup or when GSR isasserted.INIT_Q2 Binary 0, 1 0 Initial value on the Q2 pin afterconfiguration startup or when GSR isasserted.SRTYPE String "SYNC" or "ASYNC” "SYNC” Set/reset type selection. "SYNC" specifiesthe behavior of the reset (R) and set (S)pins to be synchronous to the positive edgeof the C clock pin. "ASYNC" specifies anasynchronous set/reset function.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IDDR: Double Data Rate Input Register with Set, Reset-- and Clock Enable.-- Virtex-4/5-- Xilinx HDL Libraries Guide, version 11.2IDDR_inst : IDDRgeneric map (DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE"-- or "SAME_EDGE_PIPELINED"INIT_Q1 => ’0’, -- Initial value of Q1: ’0’ or ’1’INIT_Q2 => ’0’, -- Initial value of Q2: ’0’ or ’1’SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC"port map (Q1 => Q1, -- 1-bit output for positive edge of clockQ2 => Q2, -- 1-bit output for negative edge of clockC => C, -- 1-bit clock inputCE => CE, -- 1-bit clock enable inputD => D, -- 1-bit DDR data inputR => R, -- 1-bit resetS => S -- 1-bit set);-- End of IDDR_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 165

Chapter 4: About Design ElementsVerilog Instantiation Template// IDDR: Input Double Data Rate Input Register with Set, Reset// and Clock Enable.// Virtex-4/5/6// Xilinx HDL Libraries Guide, version 11.2IDDR #(.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"// or "SAME_EDGE_PIPELINED".INIT_Q1(1’b0), // Initial value of Q1: 1’b0 or 1’b1.INIT_Q2(1’b0), // Initial value of Q2: 1’b0 or 1’b1.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC") IDDR_inst (.Q1(Q1), // 1-bit output for positive edge of clock.Q2(Q2), // 1-bit output for negative edge of clock.C(C), // 1-bit clock input.CE(CE), // 1-bit clock enable input.D(D), // 1-bit DDR data input.R(R), // 1-bit reset.S(S) // 1-bit set);// End of IDDR_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs166 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsIDDR_2CLKPrimitive: Input Dual Data-Rate Register with Dual Clock InputsIntroductionThis design element is a dedicated input register designed to receive external dual data rate (DDR) signals intoXilinx® FPGAs.In general, you should only use the IDDR_2CLK for very high speed interfaces, since it requiresmore clocking resources, more power, and can imply certain placement restrictions that are not necessary whenusing the IDDR component. Alternatively, the IDDR component is easier to use, uses fewer resources, and hasfewer restrictions, though it cannot operate at the same high I/O speeds. The IDDR_2CLK is available withmodes that present the data to the FPGA fabric at the time and clock edge they are captured, or on the same clockedge. This feature allows designers to avoid additional timing complexities and resource usage.• OPPOSITE_EDGE mode - Data is presented in the classic DDR methodology. Given a DDR data andclock at pin D and C respectively, Q1 changes after every positive edge of clock C, and Q2 changes afterevery positive edge of clock CB.• SAME_EDGE mode - Data is still presented by positive edges of each clock. However, an extra register hasbeen placed in front of the CB clocked data register. This extra register is clocked with positive clock edge ofclock signal C. As a result, DDR data is now presented into the FPGA fabric at the positive edge of clock C.However, because of this feature, the data pair appears to be "separated." Q1 and Q2 no longer have pair 1 and2. Instead, the first pair presented is Pair 1 and DON’T CARE, followed by Pair 2 and 3 at the next clock cycle.• SAME_EDGE_PIPELINED mode - Presents data in a similar fashion as the SAME_EDGE mode. In order toavoid the "separated" effect of the SAME_EDGE mode, an extra register has been placed in front of the Cclocked data register. A data pair now appears at the Q1 and Q2 pin at the same time during the positive edgeof C. However, using this mode, costs you an additional cycle of latency for Q1 and Q2 signals to change.IDDR also works with SelectIO features, such as the IODELAY.Port DescriptionsPort Direction Width FunctionQ1 : Q2 Output 1 These pins are the IDDR output that connects to the FPGAfabric. Q1 is the first data pair and Q2 is the second data pair.C Input 1 Primary clock input pin used to capture the positive edgedata.CB Input 1 Secondary clock input pin (typically 180 degrees out ofphase with the primary clock) used to capture the negativeedge data.CE Input 1 When asserted Low, this port disables the output clock atport O.D Input 1 This pin is where the DDR data is presented into the IDDRmodule.This pin connects to a top-level input or bi-directionalport, and IODELAY configured for an input delay or to anappropriate input or bidirectional buffer.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 167

Chapter 4: About Design ElementsPort Direction Width FunctionR Input 1 Active high reset forcing Q1 and Q2 to a logic zero. Canbe synchronous or asynchronous based on the SRTYPEattribute.S Input 1 Active high reset forcing Q1 and Q2 to a logic one. Canbe synchronous or asynchronous based on the SRTYPEattribute.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNo• Connect the C pin to the appropriate clock source, representing the positive clock edge and CB to theclock source representing the negative clock edge.• Connect the D pin to the top-level input, or bidirectional port, an IODELAY, or an instantiated inputor bidirectional buffer.• The Q1 and Q2 pins should be connected to the appropriate data sources.• CE should be tied high when not used, or connected to the appropriate clock enable logic.• R and S pins should be tied low, if not used, or to the appropriate set or reset generation logic.• Set all attributes to the component to represent the desired behavior.• Always instantiate this component in pairs with the same clocking, and to LOC those to the appropriate Pand N I/O pair in order not to sacrifice possible I/O resources.• Always instantiate this component in the top-level hierarchy of your design, along with any otherinstantiated I/O components for the design. This helps facilitate hierarchical design flows/practices.• To minimize CLK skew, both CLK and CLKB should come from global routing (DCM / MMCM) and notfrom the local inversion. DCM / MMCM de-skews these clocks whereas the local inversion adds skew.Available AttributesAttribute Type Allowed Values Default DescriptionDDR_CLK_EDGE String"OPPOSITE_EDGE","SAME_EDGE""SAME_EDGE_PIPELINED""OPPOSITE_EDGE”DDR clock mode recovery modeselection. See Introduction for moreexplanation.INIT_Q1 Binary 0, 1 0 Initial value on the Q1 pin afterconfiguration startup or when GSR isasserted.INIT_Q2 Binary 0, 1 0 Initial value on the Q2 pin afterconfiguration startup or when GSR isasserted.SRTYPE String "SYNC" or "ASYNC” "SYNC” Set/reset type selection. SYNC"specifies the behavior of the reset (R)and set (S) pins to be synchronous tothe positive edge of the C clock pin."ASYNC" specifies an asynchronousset/reset function.Virtex-6 Libraries Guide for HDL Designs168 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with-- Set, Reset and Clock Enable.-- Virtex-5/6-- Xilinx HDL Libraries Guide, version 11.2IDDR_2CLK_inst : IDDR_2CLKgeneric map (DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE"-- or "SAME_EDGE_PIPELINED"INIT_Q1 => ’0’, -- Initial value of Q1: ’0’ or ’1’INIT_Q2 => ’0’, -- Initial value of Q2: ’0’ or ’1’SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC"port map (Q1 => Q1, -- 1-bit output for positive edge of clockQ2 => Q2, -- 1-bit output for negative edge of clockC => C, -- 1-bit primary clock inputCB => CB, -- 1-bit secondary clock inputCE => CE, -- 1-bit clock enable inputD => D, -- 1-bit DDR data inputR => R, -- 1-bit resetS => S -- 1-bit set);-- End of IDDR_2CLK_inst instantiationVerilog Instantiation Template// IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with// Set, Reset and Clock Enable.// Virtex-5, Virtex-6// Xilinx HDL Libraries Guide, version 11.2IDDR_2CLK #(.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"// or "SAME_EDGE_PIPELINED".INIT_Q1(1’b0), // Initial value of Q1: 1’b0 or 1’b1.INIT_Q2(1’b0), // Initial value of Q2: 1’b0 or 1’b1.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC") IDDR_2CLK_inst (.Q1(Q1), // 1-bit output for positive edge of clock.Q2(Q2), // 1-bit output for negative edge of clock.C(C), // 1-bit primay clock input.CB(CB), // 1-bit secondary clock input.CE(CE), // 1-bit clock enable input.D(D), // 1-bit DDR data input.R(R), // 1-bit reset.S(S) // 1-bit set);// End of IDDR_2CLK_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 169

Chapter 4: About Design ElementsIOBUFPrimitive: Bi-Directional BufferIntroductionThe design element is a bidirectional single-ended I/O Buffer used to connect internal logic to an externalbidirectional pin.Logic TableInputs Bidirectional OutputsT I IO O1 X Z X0 1 1 10 0 0 0Port DescriptionsPort Direction Width FunctionO Output 1 Buffer outputIO Inout 1 Buffer inoutI Input 1 Buffer inputT Input 1 3-State enable inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL Designs170 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionDRIVE Integer 2, 4, 6, 8, 12, 16, 24 12 Selects output drive strength (mA)for the SelectIO buffers that usethe LVTTL, LVCMOS12, LVCMOS15,LVCMOS18, LVCMOS25, or LVCMOS33interface I/O standard.IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.SLEW String "SLOW", "FAST","QUIETIO""SLOW"Sets the output rise and fall time. See theData Sheet for recommendations of thebest setting for this attribute.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IOBUF: Single-ended Bi-directional Buffer-- All devices-- Xilinx HDL Libraries Guide, version 11.2IOBUF_inst : IOBUFgeneric map (DRIVE => 12,IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,-- "0"-"12" (Spartan-3E)-- "0"-"16" (Spartan-3A)IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register,-- "AUTO", "0"-"6" (Spartan-3E)-- "AUTO", "0"-"8" (Spartan-3A)IOSTANDARD => "DEFAULT",SLEW => "SLOW")port map (O => O, -- Buffer outputIO => IO, -- Buffer inout port (connect directly to top-level port)I => I, -- Buffer inputT => T -- 3-state enable input, high=input, low=output);-- End of IOBUF_inst instantiationVerilog Instantiation Template// IOBUF: Single-ended Bi-directional Buffer// All devices// Xilinx HDL Libraries Guide, version 11.2IOBUF #(.DRIVE(12), // Specify the output drive strength.IBUF_DELAY_VALUE("0"),// Specify the amount of added input delay for the buffer,// "0"-"12" (Spartan-3E only), "0"-"16" (Spartan-3A only).IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register,// "AUTO", "0"-"6" (Spartan-3E only), "0"-"8" (Spartan-3A only).IOSTANDARD("DEFAULT"), // Specify the I/O standard.SLEW("SLOW") // Specify the output slew rate) IOBUF_inst (.O(O),.IO(IO),.I(I),.T(T));// Buffer output// Buffer inout port (connect directly to top-level port)// Buffer input// 3-state enable input, high=input, low=output// End of IOBUF_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 171

Chapter 4: About Design ElementsFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs172 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsIOBUFDSPrimitive: 3-State Differential Signaling I/O Buffer with Active Low Output EnableIntroductionThe design element is a bidirectional buffer that supports low-voltage, differential signaling. For the IOBUFDS, adesign level interface signal is represented as two distinct ports (IO and IOB), one deemed the "master" andthe other the "slave." The master and the slave are opposite phases of the same logical signal (for example,MYNET_P and MYNET_N). Optionally, a programmable differential termination feature is available to helpimprove signal integrity and reduce external components. Also available is a programmable delay is to assist inthe capturing of incoming data to the device.Logic TableInputs Bidirectional OutputsI T IO IOB OX 1 Z Z No Change0 0 0 1 0I 0 1 0 1Port DescriptionsPort Direction Width FunctionO Output 1 Buffer outputIO Inout 1 Diff_p inoutIOB Inout 1 Diff_n inoutI Input 1 Buffer inputT Input 1 3-state enable inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 173

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IOBUFDS: Differential Bi-directional Buffer-- Spartan-3/3E/3A-- Xilinx HDL Libraries Guide, version 11.2IOBUFDS_inst : IOBUFDSgeneric map (IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,-- "0"-"12" (Spartan-3E)-- "0"-"16" (Spartan-3A)IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register,-- "AUTO", "0"-"6" (Spartan-3E)-- "AUTO", "0"-"8" (Spartan-3A)IOSTANDARD => "DEFAULT")port map (O => O, -- Buffer outputIO => IO, -- Diff_p inout (connect directly to top-level port)IOB => IOB, -- Diff_n inout (connect directly to top-level port)I => I, -- Buffer inputT => T -- 3-state enable input, high=input, low=output);-- End of IOBUFDS_inst instantiationVerilog Instantiation Template// IOBUFDS: Differential Bi-directional Buffer// Virtex-4/5, Spartan-3/3E/3A// Xilinx HDL Libraries Guide, version 11.2IOBUFDS #(.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer,// "0"-"12" (Spartan-3E only), "0"-"16" (Spartan-3A only).IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register,// "AUTO", "0"-"6" (Spartan-3E only), "0"-"8" (Spartan-3A only).IOSTANDARD("DEFAULT") // Specify the I/O standard) IOBUFDS_inst (.O(O), // Buffer output.IO(IO), // Diff_p inout (connect directly to top-level port).IOB(IOB), // Diff_n inout (connect directly to top-level port).I(I), // Buffer input.T(T) // 3-state enable input, high=input, low=output);// End of IOBUFDS_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs174 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsIODELAYE1Primitive: Input and Output Fixed or Variable Delay ElementIntroductionThis design element can be used to provide a fixed delay or an adjustable delay to the input path and a fixeddelay for the output path of the Virtex®-6 FPGA. This delay can be useful for data alignment of incoming oroutgoing data to/from the chip, as well as allowing for the tracking of data alignment over process, temperature,and voltage (PVT). When used in variable mode, the input path can be adjusted for increasing and decreasingamounts of delay. The output delay path is only available in a fixed delay. The IODELAY can also be used to addadditional static or variable delay to an internal path (within the FPGA fabric). However, when IODELAY is usedthat way, this device is no longer available to the associated I/O for input or output path delays.Port DescriptionsPort Type Width FunctionC Input 1 Clock input (Must be connected for variable mode).CE Input 1 Active high enable increment/decrement function.CINVCTRL Input 1 Dynamically inverts the Clock (C) polarity.CLKIN Input 1 Clock Access into the IODELAY (from the IO CLKMUX).CNTVALUEIN[4:0] Input 5 Counter value from fabric for loadable counter application.CNTVALUEOUT[4:0] Output 5 Counter value going to fabric for monitoring purpose.DATAIN Input 1 Data input for the internal datapath delay. When DATAIN is used,IDATAIN and ODATAIN must be tied to a logic zero (ground).DATAOUT Output 1 Delayed data output from input port (connect to input datapathlogic).IDATAIN Input 1 Data input to device from the I/O (connect directly to port, I/OBuffer). When IDATAIN is used, DATAIN must be tied to a logiczero (ground).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 175

Chapter 4: About Design ElementsPort Type Width FunctionINC Input 1 Increment / Decrement tap delay.ODATAIN Input 1 Data input for the output data path from the device (connect tooutput data source). When ODATAIN is used, DATAIN must betied to a logic zero (ground).RST Input 1 Active high, synchronous reset, resets delay chain toIDELAY_VALUE / ODELAY_VALUE tap. If no value is specified,the default is 0.T Input 1 3-state input control. Tie high for input-only or internal delay ortie low for output only.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionCINVCTRL_SEL Boolean FALSE, TRUE FALSE Dynamically inverts the Clock (C) polarity.DELAY_SRC String “I”, “CLKIN”,“DATAIN”, “IO”,“O”HIGH_PERFORMANCE_MODE“I”Specifies the source to the IODELAYcomponent.• I - Connects directly to an input port orIBUF (input mode).• O - Connects to an output port or OBUF(output mode).• IO - Connects to a port.• DATAIN - Not connected to any port(internal mode).Boolean TRUE, FALSE TRUE When TRUE, this attribute reduces the outputjitter.IDELAY_TYPE String “DEFAULT“,“FIXED“,“VARIABLE“,“VAR_LOADABLE“IDELAY_VALUE Integer 0, 1, 2, 3, 4, 5, 6, 7, 8,9, 10, 11, 12, 13, 14, 15,16, 17, 18, 19, 20, 21,22, 23, 24, 25, 26, 27,28, 29, 30, 31“DEFAULT“Specifies a fixed, variable or default (eliminatehold time) input delay.0 Specifies the number of taps of delay for theinput path when in fixed mode or the initialdelay tap value for variable mode.ODELAY_TYPE String “FIXED,“VARIABLE“,“VAR_LOADABLE“ODELAY_VALUE Integer 0, 1, 2, 3, 4, 5, 6, 7, 8,9, 10, 11, 12, 13, 14, 15,16, 17, 18, 19, 20, 21,“FIXED“Specifies a fixed, variable or default (eliminatehold time) output delay.0 Specifies the number of taps of delay for theoutput path.Virtex-6 Libraries Guide for HDL Designs176 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionREFCLK_FREQUENCY1significantdigitFLOAT22, 23, 24, 25, 26, 27,28, 29, 30, 31175.0 to 225.0 200.0 When using an associated IDELAYCTRL,specifies the input reference frequency to thecomponent.SIGNAL_PATTERN String “DATA“, “CLOCK“ “DATA“ Used by the delay calculator to determinedifferent propagation delays through theIODELAY block based on the setting. DATAwill be the addition of per tap delay and pertap jitter. No jitter is introduced for clock-likesignals.VHDL Instantiation Template-- IODELAYE1: Input and Output Fixed or Variable Delay Element-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2IODELAYE1_inst : IODELAYE1generic map (CINVCTRL_SEL => FALSE,DELAY_SRC => "I",HIGH_PERFORMANCE_MODE => TRUE,IDELAY_TYPE => "DEFAULT",IDELAY_VALUE => 0,ODELAY_TYPE => "FIXED",ODELAY_VALUE => 0,REFCLK_FREQUENCY => 200.0,SIGNAL_PATTERN => "DATA")port map (-- Dynamically inverts the Clock (C) polarity.-- Specifies the source to the IODELAY component. "I" means it will be-- connected directly to an input port or IBUF (input mode), "O" means-- it will be connected to an output port or OBUF (output mode), "IO"-- means it will be connected to a port, and "DATAIN" means it will not-- be connected to any port (internal mode).-- When TRUE, this attribute reduces the output jitter.-- Specifies a fixed, variable or default (eliminate hold time) input-- delay.-- Specifies the number of taps of delay for the input path when in-- fixed mode or the initial delay tap value for variable mode.-- Specifies the number of taps of delay for the output path.-- When using an associated IDELAYCTRL, specifies the input reference-- frequency to the component.-- Used by the delay calculator to determine different propagation-- delays through the IODELAY block based on the setting. DATA will be-- the addition of per tap delay and per tap jitter. No jitter is-- introduced for clock-like signals.CNTVALUEOUT => CNTVALUEOUT, -- 5-bit Counter value going to fabric for monitoring purposeDATAOUT => DATAOUT,-- 1-bit Delayed data output from input port (connect to input datapath logic)C => C,-- 1-bit Clock input (Must be connected for variable mode)CE => CE,-- 1-bit Active high enable increment/decrement functionCINVCTRL => CINVCTRL, -- 1-bit Dynamically inverts the Clock (C) polarityCLKIN => CLKIN,-- 1-bit Clock Access into the IODELAY (from the IO CLKMUX)CNTVALUEIN => CNTVALUEIN, -- 5-bit Counter value from fabric for loadable counter applicationDATAIN => DATAIN,-- 1-bit Data input for the internal datapath delay. When DATAIN is used,-- IDATAIN and ODATAIN must be tied to a logic zero (ground).IDATAIN => IDATAIN,INC => INC,ODATAIN => ODATAIN,RST => RST,T => T-- 1-bit Data input to device from the I/O (connect directly to port, I/O-- Buffer). When IDATAIN is used, DATAIN must be tied to a logic zero-- (ground).-- 1-bit Increment / Decrement tap delay-- 1-bit Data input for the output datapath from the device (connect to-- output data source). When ODATAIN is used, DATAIN must be tied to a logic-- zero (ground).-- 1-bit Active high, synchronous reset, resets delay chain to IDELAY_VALUE/-- ODELAY_VALUE tap. If no value is specified, the default is 0.-- 1-bit 3-state input control. Tie high for input-only or internal delay or-- tie low for output only.);Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 177

Chapter 4: About Design Elements-- End of IODELAYE1_inst instantiationVerilog Instantiation Template// IODELAYE1: Input and Output Fixed or Variable Delay Element// Virtex-6// Xilinx HDL Language Template, version 11.1IODELAYE1 #(.CINVCTRL_SEL("FALSE"),// Dynamically inverts the Clock (C) polarity..DELAY_SRC("I"),// Specifies the source to the IODELAY component. "I" means it will be// connected directly to an input port or IBUF (input mode), "O" means it// will be connected to an output port or OBUF (output mode), "IO" means// it will be connected to a port, and "DATAIN" means it will not be// connected to any port (internal mode)..HIGH_PERFORMANCE_MODE("TRUE"), // When TRUE, this attribute reduces the output jitter..IDELAY_TYPE("DEFAULT"), // Specifies a fixed, variable or default (eliminate hold time) input// delay..IDELAY_VALUE(0),// Specifies the number of taps of delay for the input path when in fixed// mode or the initial delay tap value for variable mode..ODELAY_TYPE("FIXED"),.ODELAY_VALUE(0),// Specifies the number of taps of delay for the output path..REFCLK_FREQUENCY(200.0), // When using an associated IDELAYCTRL, specifies the input reference// frequency to the component..SIGNAL_PATTERN("DATA")// Used by the delay calculator to determine different propagation delays// through the IODELAY block based on the setting. DATA will be the// addition of per tap delay and per tap jitter. No jitter is introduced// for clock-like signals.)IODELAYE1_inst (.CNTVALUEOUT(CNTVALUEOUT), // 5-bit Counter value going to fabric for monitoring purpose.DATAOUT(DATAOUT),// 1-bit Delayed data output from input port (connect to input datapath logic).C(C),// 1-bit Clock input (Must be connected for variable mode).CE(CE),// 1-bit Active high enable increment/decrement function.CINVCTRL(CINVCTRL), // 1-bit Dynamically inverts the Clock (C) polarity.CLKIN(CLKIN),// 1-bit Clock Access into the IODELAY (from the IO CLKMUX).CNTVALUEIN(CNTVALUEIN),.DATAIN(DATAIN),// 5-bit Counter value from fabric for loadable counter application// 1-bit Data input for the internal datapath delay. When DATAIN is used,// IDATAIN and ODATAIN must be tied to a logic zero (ground)..IDATAIN(IDATAIN),.INC(INC),.ODATAIN(ODATAIN),.RST(RST),.T(T)// 1-bit Data input to device from the I/O (connect directly to port, I/O// Buffer). When IDATAIN is used, DATAIN must be tied to a logic zero// (ground).// 1-bit Increment / Decrement tap delay// 1-bit Data input for the output datapath from the device (connect to output// data source). When ODATAIN is used, DATAIN must be tied to a logic zero// (ground).// 1-bit Active high, synchronous reset, resets delay chain to IDELAY_VALUE/// ODELAY_VALUE tap. If no value is specified, the default is 0.// 1-bit 3-state input control. Tie high for input-only or internal delay or// tie low for output only.);// End of IODELAYE1_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs178 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsISERDESE1Primitive: Input SERial/DESerializerIntroductionThis design element is a dedicated serial-to-parallel converter with specific clocking and logic features designedto facilitate the implementation of high-speed source-synchronous applications. It avoids the additional timingcomplexities encountered when designing deserializers in the FPGA fabric.Port DescriptionsPort Type Width FunctionBITSLIP Input 1 Input data bitslip function enable.CE1 Input 1 Input data register clock enables.CE2 Input 1 Input data register clock enables.CLK Input 1 Primary clock input pin used.CLKB Input 1 Secondary clock input.• If using in single clock DDR mode (DATA_RATE="DDR"),invert the clock connected to the CLK pin and connect to theCLKB pin.• If using in dual clock mode DDR mode, connect a unique,phase shifted clock to the CLKB pin.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 179

Chapter 4: About Design ElementsPort Type Width Function• If using in single data-rate mode (DATA_RATE="SDR"), leavethis pin unconnected or connect to ground.CLKDIV Input 1 Divided clock to be used for parallelized data.D Input 1 Input data to be connected directly to the top-level input or I/Oport of the design or to an IODELAY component if additionalinput delay control is desired.DDLY Input 1 Serial input from IODELAY.DYNCLKDIVSEL Input 1 Dynamically select CLKDIV or CLKDIV_B (via an optionalinversion).DYNCLKSEL Input 1 Dynamically select CLK or CLK_B (via an optional inversion).O Output 1 Combinatorial output.OCLK Input 1 High speed output clock typically used for memory interfaces.OCLKB Input 1 Used for Async Oversampling.OFB Input 1 Feedback Path from the OLOGIC/OSERDES Output (with orwithour ODELAY).Q1 - Q6 Output 1 Registered parallelized input data.RST Input 1 Active High asynchronous reset signal for the registers of theSERDES.SHIFTIN1/SHIFTIN2SHIFTOUT1/SHIFTOUT2Input 1 If ISERDES_MODE="SLAVE" connect to the masterISERDES_NODELAY IDATASHIFTOUT1/2 outputs. This pinmust be grounded.Output 1 If ISERDES_MODE="MASTER" and two ISERDES_NODELAYare to be cascaded, connect to the slave ISERDES_NODELAYIDATASHIFTIN1/2 inputs.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionDATA_RATE String “DDR”, “SDR” “DDR” Single Data Rate or Double Data Rateoperation.DATA_WIDTH Integer 4, 2, 3, 5, 6, 7, 8, 10 4 Parallel data width selection.DYN_CLKDIV_INV_EN Boolean FALSE, TRUE FALSE Enables dynamic CLKDIV inversionfor Memory interfaces when TRUE.DYN_CLK_INV_EN Boolean FALSE, TRUE FALSE Enables dynamic CLK inversion forMemory interfaces when TRUE.DYN_OCLK_INV_EN Boolean FALSE, TRUE FALSE Enables dynamic OCLK inversion forMemory interfaces when TRUE.Virtex-6 Libraries Guide for HDL Designs180 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionINIT_Q1 Binary 1’b0 to 1’b1 1’b0 Defines the initial value of Q1 output.INIT_Q2 Binary 1’b0 to 1’b1 1’b0 Defines the initial value of Q2 output.INIT_Q3 Binary 1’b0 to 1’b1 1’b0 Defines the initial value of Q3 output.INIT_Q4 Binary 1’b0 to 1’b1 1’b0 Defines the initial value of Q4 output.INTERFACE_TYPE String “MEMORY”,“MEMORY_DDR3”,“MEMORY_QDR”,“NETWORKING”IOBDELAY String “NONE”,“BOTH”,“IBUF”,“IFD”“MEMORY”“NONE”Memory or Networking interface type.Allows the user to either have adelayed or non-delayed version of theinput to the registered (Q1 - Q6) orcombinatorial path (O) output.NUM_CE Integer 2, 1 2 Specifies the number of clock enablesused for the ISERDES_NODELAY.OFB_USED Boolean FALSE, TRUE FALSE Will select the sneak path from theOLOGIC, OSERDES.SERDES_MODE String “MASTER”,“SLAVE”“MASTER”Specify whether the ISERDES isoperating in master or slave modeswhen cascaded width expansion.SRVAL_Q1 Binary 1’b0 to 1’b1 1’b0 Defines the value of Q1 output whenthe SR is invoked.SRVAL_Q2 Binary 1’b0 to 1’b1 1’b0 Defines the value of Q2 output whenthe SR is invoked.SRVAL_Q3 Binary 1’b0 to 1’b1 1’b0 Defines the value of Q3 output whenthe SR is invoked.SRVAL_Q4 Binary 1’b0 to 1’b1 1’b0 Defines the value of Q4 output whenthe SR is invoked.VHDL Instantiation Template-- ISERDESE1: (Input SERial/DESerializer)-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2ISERDESE1_inst : ISERDESE1generic map (DATA_RATE => "DDR",DATA_WIDTH => 4,DYN_CLKDIV_INV_EN => FALSE,DYN_CLK_INV_EN => FALSE,INIT_Q1 => "0",INIT_Q2 => "0",INIT_Q3 => "0",INIT_Q4 => "0",INTERFACE_TYPE => "MEMORY",IOBDELAY => "NONE",NUM_CE => 2,OFB_USED => FALSE,SERDES_MODE => "MASTER",-- Single Data Rate or Double Data Rate operation.-- Parallel data width selection.-- Enables dynamic CLKDIV inversion for Memory interfaces when TRUE.-- Enables dynamic CLK inversion for Memory interfaces when TRUE.-- Defines the initial value of Q1 output.-- Defines the initial value of Q2 output.-- Defines the initial value of Q3 output.-- Defines the initial value of Q4 output.-- Memory or Networking interface type.-- Specifies the number of clock enables used for the ISERDES_NODELAY.-- Will select the sneak path from the OLOGIC, OSERDES.-- Specify whether the ISERDES is operating in master or slave modes when-- cascaded width expansion.SRVAL_Q1 => "0",-- Defines the value of Q1 output when the SR is invoked.SRVAL_Q2 => "0",-- Defines the value of Q2 output when the SR is invoked.SRVAL_Q3 => "0",-- Defines the value of Q3 output when the SR is invoked.SRVAL_Q4 => "0"-- Defines the value of Q4 output when the SR is invoked.)port map (O => O,-- 1-bit Combinatorial output.-- Q1 - Q6: 1-bit (each) Registered parallelized input data.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 181

Chapter 4: About Design ElementsQ1 => Q1,Q2 => Q2,Q3 => Q3,Q4 => Q4,Q5 => Q5,Q6 => Q6,-- SHIFTOUT1/SHIFTOUT2: 1-bit (each) If ISERDES_MODE="MASTER" and two ISERDES_NODELAY are to be cascaded,-- connect to the slave ISERDES_NODELAY IDATASHIFTIN1/2 inputs.SHIFTOUT1 => SHIFTOUT1,SHIFTOUT2 => SHIFTOUT2,BITSLIP => BITSLIP,-- 1-bit Input data bitslip function enable.CE1 => CE1,-- 1-bit Input data register clock enables.CE2 => CE2,-- 1-bit DITTOCLK => CLK,CLKB => CLKB,-- 1-bit Primary clock input pin used.-- 1-bit Secondary clock input. If using in single clock DDR mode-- (DATA_RATE="DDR"), invert the clock connected to the CLK pin and connect-- to the CLKB pin. If using in dual clock mode DDR mode, connect a unique,-- phase shifted clock to the CLKB pin. If using in single data-rate mode-- (DATA_RATE="SDR"), leave this pin unconnected or connect to ground.CLKDIV => CLKDIV,D => D,-- 1-bit Divided clock to be used for parallelized data.-- 1-bit Input data to be connected directly to the top-level input or I/O-- port of the design or to an IODELAY component if additional input delay-- control is desired.);DDLY => DDLY,DYNCLKDIVSEL => DYNCLKDIVSEL, -- 1-bit Dynamically select CLKDIV or CLKDIV_B (via an optional inversion).DYNCLKSEL => DYNCLKSEL, -- 1-bit Dynamically select CLK or CLK_B (via an optional inversion).OCLK => OCLK,-- 1-bit High speed output clock typically used for memory interfaces.OFB => OFB,-- 1-bit Feedback Path from the OLOGIC/OSERDES Output (w/ or w/o ODELAY).RST => RST,-- 1-bit Active high asynchronous reset signal for the registers of the-- SERDES.-- SHIFTIN1/SHIFTIN2: 1-bit (each) If ISERDES_MODE="SLAVE" connect to the master ISERDES_NODELAY-- IDATASHIFTOUT1/2 outputs. This pin must be grounded.SHIFTIN1 => SHIFTIN1,SHIFTIN2 => SHIFTIN2-- End of ISERDESE1_inst instantiationVirtex-6 Libraries Guide for HDL Designs182 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// ISERDESE1: (Input SERial/DESerializer)// Virtex-6// Xilinx HDL Language Template, version 11.1ISERDESE1 #(.DATA_RATE("DDR"),// Single Data Rate or Double Data Rate operation..DATA_WIDTH(4),// Parallel data width selection..DYN_CLKDIV_INV_EN("FALSE"), // Enables dynamic CLKDIV inversion for Memory interfaces when TRUE..DYN_CLK_INV_EN("FALSE"), // Enables dynamic CLK inversion for Memory interfaces when TRUE..INIT_Q1(1’b0),// Defines the initial value of Q1 output..INIT_Q2(1’b0),// Defines the initial value of Q2 output..INIT_Q3(1’b0),// Defines the initial value of Q3 output..INIT_Q4(1’b0),// Defines the initial value of Q4 output..INTERFACE_TYPE("MEMORY"), // Memory or Networking interface type..IOBDELAY("NONE"),.NUM_CE(2),// Specifies the number of clock enables used for the ISERDES_NODELAY..OFB_USED("FALSE"),// Will select the sneak path from the OLOGIC, OSERDES..SERDES_MODE("MASTER"), // Specify whether the ISERDES is operating in master or slave modes when// cascaded width expansion..SRVAL_Q1(1’b0),// Defines the value of Q1 output when the SR is invoked..SRVAL_Q2(1’b0),// Defines the value of Q2 output when the SR is invoked..SRVAL_Q3(1’b0),// Defines the value of Q3 output when the SR is invoked..SRVAL_Q4(1’b0)// Defines the value of Q4 output when the SR is invoked.)ISERDESE1_inst (.O(O),// 1-bit Combinatorial output.// Q1 - Q6: 1-bit (each) Registered parallelized input data..Q1(Q1),.Q2(Q2),.Q3(Q3),.Q4(Q4),.Q5(Q5),.Q6(Q6),// SHIFTOUT1/SHIFTOUT2: 1-bit (each) If ISERDES_MODE="MASTER" and two ISERDES_NODELAY are to be cascaded,// connect to the slave ISERDES_NODELAY IDATASHIFTIN1/2 inputs..SHIFTOUT1(SHIFTOUT1),.SHIFTOUT2(SHIFTOUT2),.BITSLIP(BITSLIP),// 1-bit Input data bitslip function enable..CE1(CE1),// 1-bit Input data register clock enables..CE2(CE2),// 1-bit DITTO.CLK(CLK),// 1-bit Primary clock input pin used..CLKB(CLKB),// 1-bit Secondary clock input. If using in single clock DDR mode// (DATA_RATE="DDR"), invert the clock connected to the CLK pin and connect// to the CLKB pin. If using in dual clock mode DDR mode, connect a unique,// phase shifted clock to the CLKB pin. If using in single data-rate mode// (DATA_RATE="SDR"), leave this pin unconnected or connect to ground..CLKDIV(CLKDIV),.D(D),// 1-bit Divided clock to be used for parallelized data.// 1-bit Input data to be connected directly to the top-level input or I/O// port of the design or to an IODELAY component if additional input delay// control is desired.);.DDLY(DDLY),.DYNCLKDIVSEL(DYNCLKDIVSEL), // 1-bit Dynamically select CLKDIV or CLKDIV_B (via an optional inversion)..DYNCLKSEL(DYNCLKSEL), // 1-bit Dynamically select CLK or CLK_B (via an optional inversion)..OCLK(OCLK),// 1-bit High speed output clock typically used for memory interfaces..OFB(OFB),// 1-bit Feedback Path from the OLOGIC/OSERDES Output (w/ or w/o ODELAY)..RST(RST),// 1-bit Active high asynchronous reset signal for the registers of the// SERDES.// SHIFTIN1/SHIFTIN2: 1-bit (each) If ISERDES_MODE="SLAVE" connect to the master ISERDES_NODELAY// IDATASHIFTOUT1/2 outputs. This pin must be grounded..SHIFTIN1(SHIFTIN1),.SHIFTIN2(SHIFTIN2)// End of ISERDESE1_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 183

Chapter 4: About Design ElementsFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs184 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsKEEPERPrimitive: KEEPER SymbolIntroductionThe design element is a weak keeper element that retains the value of the net connected to its bidirectional O pin.For example, if a logic 1 is being driven onto the net, KEEPER drives a weak/resistive 1 onto the net. If the netdriver is then 3-stated, KEEPER continues to drive a weak/resistive 1 onto the net.Port DescriptionsName Direction Width FunctionO Output 1-Bit Keeper outputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- KEEPER: I/O Buffer Weak Keeper-- All FPGA, CoolRunner-II-- Xilinx HDL Libraries Guide, version 11.2KEEPER_inst : KEEPERport map (O => O -- Keeper output (connect directly to top-level port));-- End of KEEPER_inst instantiationVerilog Instantiation Template// KEEPER: I/O Buffer Weak Keeper// All FPGA, CoolRunner-II// Xilinx HDL Libraries Guide, version 11.2KEEPER KEEPER_inst (.O(O) // Keeper output (connect directly to top-level port));// End of KEEPER_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 185

Chapter 4: About Design ElementsFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs186 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsLDCEPrimitive: Transparent Data Latch with Asynchronous Clear and Gate EnableIntroductionThis design element is a transparent data latch with asynchronous clear and gate enable. When the asynchronousclear input (CLR) is High, it overrides the other inputs and resets the data (Q) output Low. Q reflects the data (D)input while the gate (G) input and gate enable (GE) are High and CLR is Low. If (GE) is Low, data on (D) cannotbe latched. The data on the (D) input during the High-to-Low gate transition is stored in the latch. The data onthe (Q) output remains unchanged as long as (G) or (GE) remains low.This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.Logic TableInputsOutputsCLR GE G D Q1 X X X 00 0 X X No Change0 1 1 D D0 1 0 X No Change0 1 ↓ D DDesign Entry MethodThis design element is only for use in schematics.Available AttributesAttribute Type Allowed Values Default DescriptionINIT Binary 0, 1 0 Sets the initial value of Q output after configuration.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 187

Chapter 4: About Design ElementsLDPEPrimitive: Transparent Data Latch with Asynchronous Preset and Gate EnableIntroductionThis design element is a transparent data latch with asynchronous preset and gate enable. When theasynchronous preset (PRE) is High, it overrides the other input and presets the data (Q) output High. Q reflectsthe data (D) input while the gate (G) input and gate enable (GE) are High. The data on the (D) input during theHigh-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as(G) or (GE) remains Low.The latch is asynchronously preset, output High, when power is applied. For FPGA devices, power-on conditionsare simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding aninverter in front of the GSR input of the appropriate STARTUP_architecture symbol.Logic TableInputsOutputsPRE GE G D Q1 X X X 10 0 X X No Change0 1 1 D D0 1 0 X No Change0 1 ↓ D DDesign Entry MethodThis design element is only for use in schematics.Available AttributesAttribute Type Allowed Values Default DescriptionINIT Binary 0, 1 1 Specifies the initial value upon power-up or theassertion of GSR for the (Q) port.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs188 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsLUT5Primitive: 5-Input Lookup Table with General OutputIntroductionThis design element is a 5-input, 1-output look-up table (LUT) that can either act as an asynchronous 32-bit ROM(with 5-bit addressing) or implement any 5-input logic function. LUTs are the basic logic building blocks andare used to implement most logic functions of the design. One LUT5 is packed into a LUT6 within a slice, ortwo LUT5s can be packed into a single LUT6 with some restrictions. The functionality of the LUT5, LUT5_Land LUT5_D is the same. However, the LUT5_L and LUT5_D allow the additional specification to connect theLUT5 output signal to an internal slice or CLB connection using the LO output. The LUT5_L specifies thatthe only connections from the LUT5 will be within a slice or CLB, while the LUT5_D allows the specificationto connect the output of the LUT to both inter-slice/CLB logic and external logic as well. The LUT5 does notstate any specific output connections and should be used in all cases except where internal slice or CLB signalconnections must be implicitly specified.An INIT attribute consisting of a 32-bit hexadecimal value must be specified to indicate the LUTs logical function.The INIT value is calculated by assigning a 1 to the corresponding INIT bit value when the associated inputsare applied. For instance, a Verilog INIT value of 32’h80000000 (X"80000000" for VHDL) makes the output zerounless all of the inputs are one (a 5-input AND gate). A Verilog INIT value of 32’hfffffffe (X"FFFFFFFE" forVHDL) makes the output one unless all zeros are on the inputs (a 5-input OR gate).The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 189

Chapter 4: About Design ElementsLogic TableInputsOutputsI4 I3 I2 I1 I0 LO0 0 0 0 0 INIT[0]0 0 0 0 1 INIT[1]0 0 0 1 0 INIT[2]0 0 0 1 1 INIT[3]0 0 1 0 0 INIT[4]0 0 1 0 1 INIT[5]0 0 1 1 0 INIT[6]0 0 1 1 1 INIT[7]0 1 0 0 0 INIT[8]0 1 0 0 1 INIT[9]0 1 0 1 0 INIT[10]0 1 0 1 1 INIT[11]0 1 1 0 0 INIT[12]0 1 1 0 1 INIT[13]0 1 1 1 0 INIT[14]0 1 1 1 1 INIT[15]1 0 0 0 0 INIT[16]1 0 0 0 1 INIT[17]1 0 0 1 0 INIT[18]1 0 0 1 1 INIT[19]1 0 1 0 0 INIT[20]1 0 1 0 1 INIT[21]1 0 1 1 0 INIT[22]1 0 1 1 1 INIT[23]1 1 0 0 0 INIT[24]1 1 0 0 1 INIT[25]1 1 0 1 0 INIT[26]1 1 0 1 1 INIT[27]1 1 1 0 0 INIT[28]1 1 1 0 1 INIT[29]1 1 1 1 0 INIT[30]1 1 1 1 1 INIT[31]INIT = Binary equivalent of the hexadecimal number assigned to the INIT attributeVirtex-6 Libraries Guide for HDL Designs190 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPort DescriptionName Direction Width FunctionO Output 1 5-LUT outputI0, I1, I2, I3, I4 Input 1 LUT inputsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 32-Bit Value All zeros Specifies the logic value for the look-uptables.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- LUT5: 5-input Look-Up Table with general output-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2LUT5_inst : LUT5generic map (INIT => X"00000000") -- Specify LUT Contentsport map (O => O, -- LUT general outputI0 => I0, -- LUT inputI1 => I1, -- LUT inputI2 => I2, -- LUT inputI3 => I3, -- LUT inputI4 => I4 -- LUT input);-- End of LUT5_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 191

Chapter 4: About Design ElementsVerilog Instantiation Template// LUT5: 5-input Look-Up Table with general output// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2LUT5 #(.INIT(32’h00000000) // Specify LUT Contents) LUT5_inst (.O(O), // LUT general output.I0(I0), // LUT input.I1(I1), // LUT input.I2(I2), // LUT input.I3(I3), // LUT input.I4(I4) // LUT input);// End of LUT5_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs192 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsLUT5_DPrimitive: 5-Input Lookup Table with General and Local OutputsIntroductionThis design element is a 5-input, 1-output look-up table (LUT) that can either act as an asynchronous 32-bit ROM(with 5-bit addressing) or implement any 5-input logic function. LUTs are the basic logic building blocks and areused to implement most logic functions of the design. One LUT5 will be packed into a LUT6 within a slice, ortwo LUT5s can be packed into a single LUT6 with some restrictions. The functionality of the LUT5, LUT5_Land LUT5_D is the same. However, the LUT5_L and LUT5_D allow the additional specification to connect theLUT5 output signal to an internal slice or CLB connection using the LO output. The LUT5_L specifies thatthe only connections from the LUT5 will be within a slice or CLB, while the LUT5_D allows the specificationto connect the output of the LUT to both inter-slice/CLB logic and external logic as well. The LUT5 does notstate any specific output connections and should be used in all cases except where internal slice or CLB signalconnections must be implicitly specified.An INIT attribute consisting of a 32-bit hexadecimal value must be specified to indicate the LUTs logical function.The INIT value is calculated by assigning a 1 to the corresponding INIT bit value when the associated inputsare applied. For instance, a Verilog INIT value of 32’h80000000 (X"80000000" for VHDL) will make the outputzero unless all of the inputs are one (a 5-input AND gate). A Verilog INIT value of 32’hfffffffe (X"FFFFFFFE" forVHDL) will make the output one unless all zeros are on the inputs (a 5-input OR gate).The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting that the abovemethod. However, this method does require the code to first specify the appropriate parameters.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 193

Chapter 4: About Design ElementsLogic TableInputsOutputsI4 I3 I2 I1 I0 O LO0 0 0 0 0 INIT[0] INIT[0]0 0 0 0 1 INIT[1] INIT[1]0 0 0 1 0 INIT[2] INIT[2]0 0 0 1 1 INIT[3] INIT[3]0 0 1 0 0 INIT[4] INIT[4]0 0 1 0 1 INIT[5] INIT[5]0 0 1 1 0 INIT[6] INIT[6]0 0 1 1 1 INIT[7] INIT[7]0 1 0 0 0 INIT[8] INIT[8]0 1 0 0 1 INIT[9] INIT[9]0 1 0 1 0 INIT[10] INIT[10]0 1 0 1 1 INIT[11] INIT[11]0 1 1 0 0 INIT[12] INIT[12]0 1 1 0 1 INIT[13] INIT[13]0 1 1 1 0 INIT[14] INIT[14]0 1 1 1 1 INIT[15] INIT[15]1 0 0 0 0 INIT[16] INIT[16]1 0 0 0 1 INIT[17] INIT[17]1 0 0 1 0 INIT[18] INIT[18]1 0 0 1 1 INIT[19] INIT[19]1 0 1 0 0 INIT[20] INIT[20]1 0 1 0 1 INIT[21] INIT[21]1 0 1 1 0 INIT[22] INIT[22]1 0 1 1 1 INIT[23] INIT[23]1 1 0 0 0 INIT[24] INIT[24]1 1 0 0 1 INIT[25] INIT[25]1 1 0 1 0 INIT[26] INIT[26]1 1 0 1 1 INIT[27] INIT[27]1 1 1 0 0 INIT[28] INIT[28]1 1 1 0 1 INIT[29] INIT[29]1 1 1 1 0 INIT[30] INIT[30]1 1 1 1 1 INIT[31] INIT[31]INIT = Binary equivalent of the hexadecimal number assigned to the INIT attributeVirtex-6 Libraries Guide for HDL Designs194 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPort DescriptionName Direction Width FunctionO Output 1 5-LUT outputL0 Output 1 5-LUT output for internal CLB connectionI0, I1, I2, I3, I4 Input 1 LUT inputsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 32-Bit Value All zeros Specifies the logic value for the look-uptables.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- LUT5: 5-input Look-Up Table with general output-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2LUT5_inst : LUT5generic map (INIT => X"00000000") -- Specify LUT Contentsport map (O => O, -- LUT general outputI0 => I0, -- LUT inputI1 => I1, -- LUT inputI2 => I2, -- LUT inputI3 => I3, -- LUT inputI4 => I4 -- LUT input);-- End of LUT5_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 195

Chapter 4: About Design ElementsVerilog Instantiation Template// LUT5: 5-input Look-Up Table with general output// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2LUT5 #(.INIT(32’h00000000) // Specify LUT Contents) LUT5_inst (.O(O), // LUT general output.I0(I0), // LUT input.I1(I1), // LUT input.I2(I2), // LUT input.I3(I3), // LUT input.I4(I4) // LUT input);// End of LUT5_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs196 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsLUT5_LPrimitive: 5-Input Lookup Table with Local OutputIntroductionThis design element is a 5-input, 1-output look-up table (LUT) that can either act as an asynchronous 32-bit ROM(with 5-bit addressing) or implement any 5-input logic function. LUTs are the basic logic building blocks and areused to implement most logic functions of the design. One LUT5 will be packed into a LUT6 within a slice, ortwo LUT5s can be packed into a single LUT6 with some restrictions. The functionality of the LUT5, LUT5_Land LUT5_D is the same. However, the LUT5_L and LUT5_D allow the additional specification to connectthe LUT5 output signal to an internal slice or CLB connection using the LO output. The LUT5_L specifiesthat the only connections from the LUT5 is within a slice or CLB, while the LUT5_D allows the specificationto connect the output of the LUT to both inter-slice/CLB logic and external logic as well. The LUT5 does notstate any specific output connections and should be used in all cases except where internal slice or CLB signalconnections must be implicitly specified.An INIT attribute consisting of a 32-bit hexadecimal value must be specified to indicate the LUTs logical function.The INIT value is calculated by assigning a 1 to the corresponding INIT bit value when the associated inputsare applied. For instance, a Verilog INIT value of 32’h80000000 (X"80000000" for VHDL) makes the output zerounless all of the inputs are one (a 5-input AND gate). A Verilog INIT value of 32’hfffffffe (X"FFFFFFFE" forVHDL) makes the output one unless all zeros are on the inputs (a 5-input OR gate).The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed logic value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 197

Chapter 4: About Design ElementsLogic TableInputsOutputsI4 I3 I2 I1 I0 LO0 0 0 0 0 INIT[0]0 0 0 0 1 INIT[1]0 0 0 1 0 INIT[2]0 0 0 1 1 INIT[3]0 0 1 0 0 INIT[4]0 0 1 0 1 INIT[5]0 0 1 1 0 INIT[6]0 0 1 1 1 INIT[7]0 1 0 0 0 INIT[8]0 1 0 0 1 INIT[9]0 1 0 1 0 INIT[10]0 1 0 1 1 INIT[11]0 1 1 0 0 INIT[12]0 1 1 0 1 INIT[13]0 1 1 1 0 INIT[14]0 1 1 1 1 INIT[15]1 0 0 0 0 INIT[16]1 0 0 0 1 INIT[17]1 0 0 1 0 INIT[18]1 0 0 1 1 INIT[19]1 0 1 0 0 INIT[20]1 0 1 0 1 INIT[21]1 0 1 1 0 INIT[22]1 0 1 1 1 INIT[23]1 1 0 0 0 INIT[24]1 1 0 0 1 INIT[25]1 1 0 1 0 INIT[26]1 1 0 1 1 INIT[27]1 1 1 0 0 INIT[28]1 1 1 0 1 INIT[29]1 1 1 1 0 INIT[30]1 1 1 1 1 INIT[31]INIT = Binary equivalent of the hexadecimal number assigned to the INIT attributeVirtex-6 Libraries Guide for HDL Designs198 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPort DescriptionName Direction Width FunctionL0 Output 1 6/5-LUT output for internal CLB connectionI0, I1, I2, I3, I4 Input 1 LUT inputsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 32-Bit Value All zeros Specifies the logic value for the look-uptables.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- LUT5: 5-input Look-Up Table with general output-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2LUT5_inst : LUT5generic map (INIT => X"00000000") -- Specify LUT Contentsport map (O => O, -- LUT general outputI0 => I0, -- LUT inputI1 => I1, -- LUT inputI2 => I2, -- LUT inputI3 => I3, -- LUT inputI4 => I4 -- LUT input);-- End of LUT5_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 199

Chapter 4: About Design ElementsVerilog Instantiation Template// LUT5: 5-input Look-Up Table with general output// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2LUT5 #(.INIT(32’h00000000) // Specify LUT Contents) LUT5_inst (.O(O), // LUT general output.I0(I0), // LUT input.I1(I1), // LUT input.I2(I2), // LUT input.I3(I3), // LUT input.I4(I4) // LUT input);// End of LUT5_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs200 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsLUT6Primitive: 6-Input Lookup Table with General OutputIntroductionThis design element is a 6-input, 1-output look-up table (LUT) that can either act as an asynchronous 64-bit ROM(with 6-bit addressing) or implement any 6-input logic function. LUTs are the basic logic building blocks and areused to implement most logic functions of the design. A LUT6 is mapped to one of the four look-up tables in theslice. The functionality of the LUT6, LUT6_L and LUT6_D is the same. However, the LUT6_L and LUT6_D allowthe additional specification to connect the LUT6 output signal to an internal slice, or CLB connection, using theLO output. The LUT6_L specifies that the only connections from the LUT6 will be within a slice, or CLB, whilethe LUT6_D allows the specification to connect the output of the LUT to both inter-slice/CLB logic and externallogic as well. The LUT6 does not state any specific output connections and should be used in all cases exceptwhere internal slice or CLB signal connections must be implicitly specified.An INIT attribute consisting of a 64-bit Hexadecimal value must be specified to indicate the LUTs logical function.The INIT value is calculated by assigning a 1 to corresponding INIT bit value when the associated inputs areapplied. For instance, a Verilog INIT value of 64’h8000000000000000 (X"8000000000000000" for VHDL) makesthe output zero unless all of the inputs are one (a 6-input AND gate). A Verilog INIT value of 64’hfffffffffffffffe(X"FFFFFFFFFFFFFFFE" for VHDL) makes the output one unless all zeros are on the inputs (a 6-input OR gate).The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.Logic TableInputsI5 I4 I3 I2 I1 I0 OOutputs0 0 0 0 0 0 INIT[0]0 0 0 0 0 1 INIT[1]0 0 0 0 1 0 INIT[2]Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 201

Chapter 4: About Design ElementsInputsOutputsI5 I4 I3 I2 I1 I0 O0 0 0 0 1 1 INIT[3]0 0 0 1 0 0 INIT[4]0 0 0 1 0 1 INIT[5]0 0 0 1 1 0 INIT[6]0 0 0 1 1 1 INIT[7]0 0 1 0 0 0 INIT[8]0 0 1 0 0 1 INIT[9]0 0 1 0 1 0 INIT[10]0 0 1 0 1 1 INIT[11]0 0 1 1 0 0 INIT[12]0 0 1 1 0 1 INIT[13]0 0 1 1 1 0 INIT[14]0 0 1 1 1 1 INIT[15]0 1 0 0 0 0 INIT[16]0 1 0 0 0 1 INIT[17]0 1 0 0 1 0 INIT[18]0 1 0 0 1 1 INIT[19]0 1 0 1 0 0 INIT[20]0 1 0 1 0 1 INIT[21]0 1 0 1 1 0 INIT[22]0 1 0 1 1 1 INIT[23]0 1 1 0 0 0 INIT[24]0 1 1 0 0 1 INIT[25]0 1 1 0 1 0 INIT[26]0 1 1 0 1 1 INIT[27]0 1 1 1 0 0 INIT[28]0 1 1 1 0 1 INIT[29]0 1 1 1 1 0 INIT[30]0 1 1 1 1 1 INIT[31]1 0 0 0 0 0 INIT[32]1 0 0 0 0 1 INIT[33]1 0 0 0 1 0 INIT[34]1 0 0 0 1 1 INIT[35]1 0 0 1 0 0 INIT[36]1 0 0 1 0 1 INIT[37]1 0 0 1 1 0 INIT[38]1 0 0 1 1 1 INIT[39]1 0 1 0 0 0 INIT[40]Virtex-6 Libraries Guide for HDL Designs202 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsInputsOutputsI5 I4 I3 I2 I1 I0 O1 0 1 0 0 1 INIT[41]1 0 1 0 1 0 INIT[42]1 0 1 0 1 1 INIT[43]1 0 1 1 0 0 INIT[44]1 0 1 1 0 1 INIT[45]1 0 1 1 1 0 INIT[46]1 0 1 1 1 1 INIT[47]1 1 0 0 0 0 INIT[48]1 1 0 0 0 1 INIT[49]1 1 0 0 1 0 INIT[50]1 1 0 0 1 1 INIT[51]1 1 0 1 0 0 INIT[52]1 1 0 1 0 1 INIT[53]1 1 0 1 1 0 INIT[54]1 1 0 1 1 1 INIT[55]1 1 1 0 0 0 INIT[56]1 1 1 0 0 1 INIT[57]1 1 1 0 1 0 INIT[58]1 1 1 0 1 1 INIT[59]1 1 1 1 0 0 INIT[60]1 1 1 1 0 1 INIT[61]1 1 1 1 1 0 INIT[62]1 1 1 1 1 1 INIT[63]INIT = Binary equivalent of the hexadecimal number assigned to the INIT attributePort DescriptionName Direction Width FunctionO Output 1 6/5-LUT outputI0, I1, I2, I3, I4, I5 Input 1 LUT inputsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 203

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 64-Bit Value All zeros Specifies the logic value for thelook-up tables.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- LUT6: 6-input Look-Up Table with general output-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2LUT6_inst : LUT6generic map (INIT => X"0000000000000000") -- Specify LUT Contentsport map (O => O, -- LUT general outputI0 => I0, -- LUT inputI1 => I1, -- LUT inputI2 => I2, -- LUT inputI3 => I3, -- LUT inputI4 => I4, -- LUT inputI5 => I5 -- LUT input);-- End of LUT6_inst instantiationVerilog Instantiation Template// LUT6: 6-input Look-Up Table with general output// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2LUT6 #(.INIT(64’h0000000000000000) // Specify LUT Contents) LUT6_inst (.O(O), // LUT general output.I0(I0), // LUT input.I1(I1), // LUT input.I2(I2), // LUT input.I3(I3), // LUT input.I4(I4), // LUT input.I5(I5) // LUT input);// End of LUT6_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs204 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsLUT6_2Primitive: Six-input, 2-output, Look-Up TableIntroductionThis design element is a 6-input, 2-output look-up table (LUT) that can either act as a dual asynchronous 32-bitROM (with 5-bit addressing), implement any two 5-input logic functions with shared inputs, or implement a6-input logic function and a 5-input logic function with shared inputs and shared logic values. LUTs are thebasic logic building blocks and are used to implement most logic functions of the design. A LUT6_2 will bemapped to one of the four look-up tables in the slice.An INIT attribute consisting of a 64-bit hexadecimal value must be specified to indicate the LUTs logical function.The INIT value is calculated by assigning a 1 to corresponding INIT bit value when the associated inputs areapplied. For instance, a Verilog INIT value of 64’hfffffffffffffffe (X"FFFFFFFFFFFFFFFE" for VHDL) makes the O6output 1 unless all zeros are on the inputs and the O5 output a 1, or unless I[4:0] are all zeroes (a 5-input and6-input OR gate). The lower half (bits 31:0) of the INIT values apply to the logic function of the O5 output.The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.Logic TableInputsOutputsI5 I4 I3 I2 I1 I0 O5 O60 0 0 0 0 0 INIT[0] INIT[0]0 0 0 0 0 1 INIT[1] INIT[1]0 0 0 0 1 0 INIT[2] INIT[2]0 0 0 0 1 1 INIT[3] INIT[3]0 0 0 1 0 0 INIT[4] INIT[4]Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 205

Chapter 4: About Design ElementsInputsOutputs0 0 0 1 0 1 INIT[5] INIT[5]0 0 0 1 1 0 INIT[6] INIT[6]0 0 0 1 1 1 INIT[7] INIT[7]0 0 1 0 0 0 INIT[8] INIT[8]0 0 1 0 0 1 INIT[9] INIT[9]0 0 1 0 1 0 INIT[10] INIT[10]0 0 1 0 1 1 INIT[11] INIT[11]0 0 1 1 0 0 INIT[12] INIT[12]0 0 1 1 0 1 INIT[13] INIT[13]0 0 1 1 1 0 INIT[14] INIT[14]0 0 1 1 1 1 INIT[15] INIT[15]0 1 0 0 0 0 INIT[16] INIT[16]0 1 0 0 0 1 INIT[17] INIT[17]0 1 0 0 1 0 INIT[18] INIT[18]0 1 0 0 1 1 INIT[19] INIT[19]0 1 0 1 0 0 INIT[20] INIT[20]0 1 0 1 0 1 INIT[21] INIT[21]0 1 0 1 1 0 INIT[22] INIT[22]0 1 0 1 1 1 INIT[23] INIT[23]0 1 1 0 0 0 INIT[24] INIT[24]0 1 1 0 0 1 INIT[25] INIT[25]0 1 1 0 1 0 INIT[26] INIT[26]0 1 1 0 1 1 INIT[27] INIT[27]0 1 1 1 0 0 INIT[28] INIT[28]0 1 1 1 0 1 INIT[29] INIT[29]0 1 1 1 1 0 INIT[30] INIT[30]0 1 1 1 1 1 INIT[31] INIT[31]1 0 0 0 0 0 INIT[0] INIT[32]1 0 0 0 0 1 INIT[1] INIT[33]1 0 0 0 1 0 INIT[2] INIT[34]1 0 0 0 1 1 INIT[3] INIT[35]1 0 0 1 0 0 INIT[4] INIT[36]1 0 0 1 0 1 INIT[5] INIT[37]1 0 0 1 1 0 INIT[6] INIT[38]1 0 0 1 1 1 INIT[7] INIT[39]1 0 1 0 0 0 INIT[8] INIT[40]1 0 1 0 0 1 INIT[9] INIT[41]1 0 1 0 1 0 INIT[10] INIT[42]1 0 1 0 1 1 INIT[11] INIT[43]Virtex-6 Libraries Guide for HDL Designs206 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsInputsOutputs1 0 1 1 0 0 INIT[12] INIT[44]1 0 1 1 0 1 INIT[13] INIT[45]1 0 1 1 1 0 INIT[14] INIT[46]1 0 1 1 1 1 INIT[15] INIT[47]1 1 0 0 0 0 INIT[16] INIT[48]1 1 0 0 0 1 INIT[17] INIT[49]1 1 0 0 1 0 INIT[18] INIT[50]1 1 0 0 1 1 INIT[19] INIT[51]1 1 0 1 0 0 INIT[20] INIT[52]1 1 0 1 0 1 INIT[21] INIT[53]1 1 0 1 1 0 INIT[22] INIT[54]1 1 0 1 1 1 INIT[23] INIT[55]1 1 1 0 0 0 INIT[24] INIT[56]1 1 1 0 0 1 INIT[25] INIT[57]1 1 1 0 1 0 INIT[26] INIT[58]1 1 1 0 1 1 INIT[27] INIT[59]1 1 1 1 0 0 INIT[28] INIT[60]1 1 1 1 0 1 INIT[29] INIT[61]1 1 1 1 1 0 INIT[30] INIT[62]1 1 1 1 1 1 INIT[31] INIT[63]INIT = Binary equivalent of the hexadecimal number assigned to the INIT attributePort DescriptionsPort Direction Width FunctionO6 Output 1 6/5-LUT outputO5 Output 1 5-LUT outputI0, I1, I2, I3, I4, I5 Input 1 LUT inputsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 64-Bit Value All zeros Specifies the LUT5/6 output function.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 207

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- LUT6_2: 6-input 2 output Look-Up Table-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2LUT6_2_inst : LUT6_2generic map (INIT => X"0000000000000000") -- Specify LUT Contentsport map (O6 => O6, -- 6/5-LUT output (1-bit)O5 => O5, -- 5-LUT output (1-bit)I0 => I0, -- LUT input (1-bit)I1 => I1, -- LUT input (1-bit)I2 => I2, -- LUT input (1-bit)I3 => I3, -- LUT input (1-bit)I4 => I4, -- LUT input (1-bit)I5 => I5 -- LUT input (1-bit));-- End of LUT6_2_inst instantiationVerilog Instantiation Template// LUT6_2: 6-input, 2 output Look-Up Table// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2LUT6_2 #(.INIT(64’h0000000000000000) // Specify LUT Contents) LUT6_2_inst (.O6(O6), // 6/5-LUT output (1-bit).O5(O5), // 5-LUT output (1-bit).I0(I0), // LUT input (1-bit).I1(I1), // LUT input (1-bit).I2(I2), // LUT input (1-bit).I3(I3), // LUT input (1-bit).I4(I4), // LUT input (1-bit).I5(I5) // LUT input (1-bit));// End of LUT6_2_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs208 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsLUT6_DPrimitive: 6-Input Lookup Table with General and Local OutputsIntroductionThis design element is a six-input, one-output look-up table (LUT) that can either act as an asynchronous 64-bitROM (with 6-bit addressing) or implement any 6-input logic function. LUTs are the basic logic building blocksand are used to implement most logic functions of the design. A LUT6 is mapped to one of the four look-uptables in the slice. The functionality of the LUT6, LUT6_L and LUT6_D is the same. However, the LUT6_Land LUT6_D allow the additional specification to connect the LUT6 output signal to an internal slice, or CLBconnection, using the LO output. The LUT6_L specifies that the only connections from the LUT6 will be within aslice, or CLB, while the LUT6_D allows the specification to connect the output of the LUT to both inter-slice/CLBlogic and external logic as well. The LUT6 does not state any specific output connections and should be used inall cases except where internal slice or CLB signal connections must be implicitly specified.An INIT attribute consisting of a 64-bit Hexadecimal value must be specified to indicate the LUTs logical function.The INIT value is calculated by assigning a 1 to corresponding INIT bit value when the associated inputs areapplied. For instance, a Verilog INIT value of 64’h8000000000000000 (X"8000000000000000" for VHDL) makesthe output zero unless all of the inputs are one (a 6-input AND gate). A Verilog INIT value of 64’hfffffffffffffffe(X"FFFFFFFFFFFFFFFE" for VHDL) makes the output one unless all zeros are on the inputs (a 6-input OR gate).The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more is self-documenting that the abovemethod. However, this method does require the code to first specify the appropriate parameters.Logic TableInputsOutputsI5 I4 I3 I2 I1 I0 O LO0 0 0 0 0 0 INIT[0] INIT[0]0 0 0 0 0 1 INIT[1] INIT[1]0 0 0 0 1 0 INIT[2] INIT[2]Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 209

Chapter 4: About Design ElementsInputsOutputsI5 I4 I3 I2 I1 I0 O LO0 0 0 0 1 1 INIT[3] INIT[3]0 0 0 1 0 0 INIT[4] INIT[4]0 0 0 1 0 1 INIT[5] INIT[5]0 0 0 1 1 0 INIT[6] INIT[6]0 0 0 1 1 1 INIT[7] INIT[7]0 0 1 0 0 0 INIT[8] INIT[8]0 0 1 0 0 1 INIT[9] INIT[9]0 0 1 0 1 0 INIT[10] INIT[10]0 0 1 0 1 1 INIT[11] INIT[11]0 0 1 1 0 0 INIT[12] INIT[12]0 0 1 1 0 1 INIT[13] INIT[13]0 0 1 1 1 0 INIT[14] INIT[14]0 0 1 1 1 1 INIT[15] INIT[15]0 1 0 0 0 0 INIT[16] INIT[16]0 1 0 0 0 1 INIT[17] INIT[17]0 1 0 0 1 0 INIT[18] INIT[18]0 1 0 0 1 1 INIT[19] INIT[19]0 1 0 1 0 0 INIT[20] INIT[20]0 1 0 1 0 1 INIT[21] INIT[21]0 1 0 1 1 0 INIT[22] INIT[22]0 1 0 1 1 1 INIT[23] INIT[23]0 1 1 0 0 0 INIT[24] INIT[24]0 1 1 0 0 1 INIT[25] INIT[25]0 1 1 0 1 0 INIT[26] INIT[26]0 1 1 0 1 1 INIT[27] INIT[27]0 1 1 1 0 0 INIT[28] INIT[28]0 1 1 1 0 1 INIT[29] INIT[29]0 1 1 1 1 0 INIT[30] INIT[30]0 1 1 1 1 1 INIT[31] INIT[31]1 0 0 0 0 0 INIT[32] INIT[32]1 0 0 0 0 1 INIT[33] INIT[33]1 0 0 0 1 0 INIT[34] INIT[34]1 0 0 0 1 1 INIT[35] INIT[35]1 0 0 1 0 0 INIT[36] INIT[36]1 0 0 1 0 1 INIT[37] INIT[37]1 0 0 1 1 0 INIT[38] INIT[38]1 0 0 1 1 1 INIT[39] INIT[39]1 0 1 0 0 0 INIT[40] INIT[40]Virtex-6 Libraries Guide for HDL Designs210 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsInputsOutputsI5 I4 I3 I2 I1 I0 O LO1 0 1 0 0 1 INIT[41] INIT[41]1 0 1 0 1 0 INIT[42] INIT[42]1 0 1 0 1 1 INIT[43] INIT[43]1 0 1 1 0 0 INIT[44] INIT[44]1 0 1 1 0 1 INIT[45] INIT[45]1 0 1 1 1 0 INIT[46] INIT[46]1 0 1 1 1 1 INIT[47] INIT[47]1 1 0 0 0 0 INIT[48] INIT[48]1 1 0 0 0 1 INIT[49] INIT[49]1 1 0 0 1 0 INIT[50] INIT[50]1 1 0 0 1 1 INIT[51] INIT[51]1 1 0 1 0 0 INIT[52] INIT[52]1 1 0 1 0 1 INIT[53] INIT[53]1 1 0 1 1 0 INIT[54] INIT[54]1 1 0 1 1 1 INIT[55] INIT[55]1 1 1 0 0 0 INIT[56] INIT[56]1 1 1 0 0 1 INIT[57] INIT[57]1 1 1 0 1 0 INIT[58] INIT[58]1 1 1 0 1 1 INIT[59] INIT[59]1 1 1 1 0 0 INIT[60] INIT[60]1 1 1 1 0 1 INIT[61] INIT[61]1 1 1 1 1 0 INIT[62] INIT[62]1 1 1 1 1 1 INIT[63] INIT[63]INIT = Binary equivalent of the hexadecimal number assigned to the INIT attributePort DescriptionName Direction Width FunctionO6 Output 1 6/5-LUT outputO5 Output 1 5-LUT outputI0, I1, I2, I3, I4, I5 Input 1 LUT inputsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 211

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 64-Bit Value All zeros Specifies the logic value for the look-uptables.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- LUT6: 6-input Look-Up Table with general output-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2LUT6_inst : LUT6generic map (INIT => X"0000000000000000") -- Specify LUT Contentsport map (O => O, -- LUT general outputI0 => I0, -- LUT inputI1 => I1, -- LUT inputI2 => I2, -- LUT inputI3 => I3, -- LUT inputI4 => I4, -- LUT inputI5 => I5 -- LUT input);-- End of LUT6_inst instantiationVerilog Instantiation Template// LUT6: 6-input Look-Up Table with general output// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2LUT6 #(.INIT(64’h0000000000000000) // Specify LUT Contents) LUT6_inst (.O(O), // LUT general output.I0(I0), // LUT input.I1(I1), // LUT input.I2(I2), // LUT input.I3(I3), // LUT input.I4(I4), // LUT input.I5(I5) // LUT input);// End of LUT6_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs212 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsLUT6_LPrimitive: 6-Input Lookup Table with Local OutputIntroductionThis design element is a 6-input, 1-output look-up table (LUT) that can either act as an asynchronous 64-bit ROM(with 6-bit addressing) or implement any 6-input logic function. LUTs are the basic logic building blocks and areused to implement most logic functions of the design. A LUT6 is mapped to one of the four look-up tables inthe slice. The functionality of the LUT6, LUT6_L and LUT6_D is the same. However, the LUT6_L and LUT6_Dallow the additional specification to connect the LUT6 output signal to an internal slice, or CLB connection, usingthe LO output. The LUT6_L specifies that the only connections from the LUT6 are within a slice, or CLB, whilethe LUT6_D allows the specification to connect the output of the LUT to both inter-slice/CLB logic and externallogic as well. The LUT6 does not state any specific output connections and should be used in all cases exceptwhere internal slice or CLB signal connections must be implicitly specified.An INIT attribute consisting of a 64-bit hexadecimal value must be specified to indicate the LUT’s logicalfunction. The INIT value is calculated by assigning a 1 to the corresponding INIT bit value when the associatedinputs are applied. For instance, a Verilog INIT value of 64’h8000000000000000 (X"8000000000000000" forVHDL) will make the output zero unless all of the inputs are one (a 6-input AND gate). A Verilog INIT valueof 64’hfffffffffffffffe (X"FFFFFFFFFFFFFFFE" for VHDL) will make the output one unless all zeros are on theinputs (a 6-input OR gate).The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting that the abovemethod. However, this method does require the code to first specify the appropriate parameters.Logic TableInputsI5 I4 I3 I2 I1 I0 LOOutputs0 0 0 0 0 0 INIT[0]0 0 0 0 0 1 INIT[1]Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 213

Chapter 4: About Design ElementsInputsOutputsI5 I4 I3 I2 I1 I0 LO0 0 0 0 1 0 INIT[2]0 0 0 0 1 1 INIT[3]0 0 0 1 0 0 INIT[4]0 0 0 1 0 1 INIT[5]0 0 0 1 1 0 INIT[6]0 0 0 1 1 1 INIT[7]0 0 1 0 0 0 INIT[8]0 0 1 0 0 1 INIT[9]0 0 1 0 1 0 INIT[10]0 0 1 0 1 1 INIT[11]0 0 1 1 0 0 INIT[12]0 0 1 1 0 1 INIT[13]0 0 1 1 1 0 INIT[14]0 0 1 1 1 1 INIT[15]0 1 0 0 0 0 INIT[16]0 1 0 0 0 1 INIT[17]0 1 0 0 1 0 INIT[18]0 1 0 0 1 1 INIT[19]0 1 0 1 0 0 INIT[20]0 1 0 1 0 1 INIT[21]0 1 0 1 1 0 INIT[22]0 1 0 1 1 1 INIT[23]0 1 1 0 0 0 INIT[24]0 1 1 0 0 1 INIT[25]0 1 1 0 1 0 INIT[26]0 1 1 0 1 1 INIT[27]0 1 1 1 0 0 INIT[28]0 1 1 1 0 1 INIT[29]0 1 1 1 1 0 INIT[30]0 1 1 1 1 1 INIT[31]1 0 0 0 0 0 INIT[32]1 0 0 0 0 1 INIT[33]1 0 0 0 1 0 INIT[34]1 0 0 0 1 1 INIT[35]1 0 0 1 0 0 INIT[36]1 0 0 1 0 1 INIT[37]1 0 0 1 1 0 INIT[38]1 0 0 1 1 1 INIT[39]Virtex-6 Libraries Guide for HDL Designs214 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsInputsOutputsI5 I4 I3 I2 I1 I0 LO1 0 1 0 0 0 INIT[40]1 0 1 0 0 1 INIT[41]1 0 1 0 1 0 INIT[42]1 0 1 0 1 1 INIT[43]1 0 1 1 0 0 INIT[44]1 0 1 1 0 1 INIT[45]1 0 1 1 1 0 INIT[46]1 0 1 1 1 1 INIT[47]1 1 0 0 0 0 INIT[48]1 1 0 0 0 1 INIT[49]1 1 0 0 1 0 INIT[50]1 1 0 0 1 1 INIT[51]1 1 0 1 0 0 INIT[52]1 1 0 1 0 1 INIT[53]1 1 0 1 1 0 INIT[54]1 1 0 1 1 1 INIT[55]1 1 1 0 0 0 INIT[56]1 1 1 0 0 1 INIT[57]1 1 1 0 1 0 INIT[58]1 1 1 0 1 1 INIT[59]1 1 1 1 0 0 INIT[60]1 1 1 1 0 1 INIT[61]1 1 1 1 1 0 INIT[62]1 1 1 1 1 1 INIT[63]INIT = Binary equivalent of the hexadecimal number assigned to the INIT attributePort DescriptionName Direction Width FunctionLO Output 1 6/5-LUT output or internal CLB connectionI0, I1, I2, I3, I4, I5 Input 1 LUT inputsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 215

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 64-Bit Value All zeros Specifies the logic value for thelook-up tables.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- LUT6: 6-input Look-Up Table with general output-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2LUT6_inst : LUT6generic map (INIT => X"0000000000000000") -- Specify LUT Contentsport map (O => O, -- LUT general outputI0 => I0, -- LUT inputI1 => I1, -- LUT inputI2 => I2, -- LUT inputI3 => I3, -- LUT inputI4 => I4, -- LUT inputI5 => I5 -- LUT input);-- End of LUT6_inst instantiationVerilog Instantiation Template// LUT6: 6-input Look-Up Table with general output// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2LUT6 #(.INIT(64’h0000000000000000) // Specify LUT Contents) LUT6_inst (.O(O), // LUT general output.I0(I0), // LUT input.I1(I1), // LUT input.I2(I2), // LUT input.I3(I3), // LUT input.I4(I4), // LUT input.I5(I5) // LUT input);// End of LUT6_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs216 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsMMCM_ADVPrimitive: MMCM is a mixed signal block designed to support clock network deskew, frequencysynthesis, and jitter reduction.IntroductionThis component is a mixed signal block designed to support clock network deskew, frequency synthesis,and jitter reduction. The seven "O" counters can be independently programmed, which means O0 could beprogrammed to do a divide by 2 while O1 is programmed to do a divide by 3. The only limitation is that theVCO operating frequency must be the same for all the output counters since a single VCO drives all the counters.The CLKFBOUT and CLKFBOUTB can be used to drive logic, but it must be equal to the CLKin frequencydivided by the value of the DIVCLK_DIVIDE attribute.Port DescriptionsPort Type Width FunctionCLKFBIN Input 1 Feedback clock input.CLKFBOUT Output 1 Dedicated MMCM feedback output.CLKFBOUTB Output 1 Inverted MMCM feedback clock output.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 217

Chapter 4: About Design ElementsPort Type Width FunctionCLKFBSTOPPED Output 1 Status pin indicating that the feedback clock has stopped.CLKINSEL Input 1 Signal controls the state of the clock input MUX, High = CLKIN1,Low = CLKIN2. Dynamically switches the MMCM reference clock.CLKINSTOPPED Output 1 Status pin indicating that the input clock has stopped.CLKIN1 Input 1 General clock input.CLKIN2 Input 1 Secondary clock input for the MMCM reference clock.CLKOUT[0:6] Output 7, 1–bit User configurable clock outputs (0 through 6) that can be dividedversions of the VCO phase outputs (user controllable) from 1(bypassed) to 128. The output clocks are phase aligned to eachother (unless phase shifted) and aligned to the input clock with aproper feedback configuration.CLKOUT[0:3]B Output 4, 1–bit Inverted CLKOUT[0:3].DADDR[6:0] Input 7 The dynamic reconfiguration address (DADDR) inputbus provides a reconfiguration address for the dynamicreconfiguration. When not used, all bits must be assigned zeros.DCLK Input 1 The DCLK signal is the reference clock for the dynamicreconfiguration port.DEN Input 1 The dynamic reconfiguration enable (DEN) provides the enablecontrol signal to access the dynamic reconfiguration feature.When the dynamic reconfiguration feature is not used, DEN mustbe tied Low.DI[15:0] Input 16 The dynamic reconfiguration data input (DI) bus providesreconfiguration data. When not used, all bits must be set to zero.DO[15:0] Output 16 The dynamic reconfiguration output bus provides MMCM dataoutput when using dynamic reconfiguration.DRDY Output 1 The dynamic reconfiguration ready (DRDY) output providesthe response to the DEN signal for the MMCMs dynamicreconfiguration feature.DWE Input 1 The dynamic reconfiguration write enable (DWE) input pinprovides the write enable control signal to write the DI data intothe DADDR address. When not used, it must be tied Low.LOCKED Output 1 An output from the MMCM that indicates when the MMCMhas achieved phase alignment within a predefined window andfrequency matching within a predefined PPM range. The MMCMautomatically locks after power on. No extra reset is required.LOCKED will be deasserted if the input clock stops or the phasealignment is violated (e.g., input clock phase shift). The MMCMautomatically reacquires lock after LOCKED is deasserted.PSCLK Input 1 Phase shift clock.PSDONE Output 1 Phase shift done.PSEN Input 1 Phase shift enable.PSINCDEC Input 1 Phase shift Increment/Decrement control.PWRDWN Input 1 Powers down instantiated but unused MMCMs.RST Input 1 Asynchronous reset signal. The RST signal is an asynchronousreset for the MMCM. The MMCM will synchronously re-enableitself when this signal is released (i.e., MMCM re-enabled). Areset is not required when the input clock conditions change (e.g.,frequency).Virtex-6 Libraries Guide for HDL Designs218 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoRecommendedNoAvailable AttributesAttribute Type Allowed Values Default DescriptionBANDWIDTH String “OPTIMIZED”,“HIGH”,“LOW”CLKFBOUT_MULT_F 3significantdigit FloatCLKFBOUT_PHASE 3significantdigit FloatCLKFBOUT_USE_FINE_PS1.000 to64.000-360.000 to360.000CLKIN1_PERIOD Float (nS) 1.000 to1000.000CLKIN2_PERIOD Float (nS) 1.000 to1000.000CLKOUT0_DIVIDE_F 3significantdigit FloatCLKOUT[0:6]_DUTY_CYCLECLKOUT[0:6]__PHASECLKOUT0_USE_FINE_PS“OPTIMIZED” Specifies the MMCM programmingalgorithm affecting the jitter, phase margin,and other characteristics of the MMCM.1.000 Specifies the amount to multiplyall CLKOUT clock outputs if adifferent frequency is desired. Thisnumber, in combination with theassociated CLKOUT#_DIVIDE value andDIVCLK_DIVIDE value, will determine theoutput frequency.0.000 Specifies the phase offset in degrees of theclock feedback output. Shifting the feedbackclock results in a negative phase shift of alloutput clocks to the MMCM.Boolean FALSE, TRUE FALSE CLKFBOUT counter variable fine phaseshift enable. CLKFBOUT_MULT must bean integer and therefore fractional divide isnot allowed.3significantdigit Float3significantdigit Float1.000 to128.0000.001 to0.999-360.000 to360.0000.000 Specifies the input period in ns to theMMCM CLKIN1 input. Resolution is downto the ps. This information is mandatoryand must be supplied.0.000 Specifies the input period in ns to theMMCM CLKIN2 input. Resolution is downto the ps. This information is mandatoryand must be supplied.1.000 Specifies the amount to divide theassociated CLKOUT clock output if adifferent frequency is desired. This numberin combination with the CLKFBOUT_MULTand DIVCLK_DIVIDE values will determinethe output frequency.0.500 Specifies the Duty Cycle of the associatedCLKOUT clock output in percentage (i.e.,0.50 will generate a 50% duty cycle).0.000 Allows specification of the output phaserelationship of the associated CLKOUTclock output in number of degrees offset(i.e., 90 indicates a 90° or ¼ cycle offsetphase offset while 180 indicates a 180° offsetor ½ cycle phase offset).Boolean FALSE, TRUE FALSE CLKOUT0 counter variable fine phase shiftenable. CLKOUT0_DIVIDE must be aninteger and therefore fractional divide is notallowed.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 219

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionCLKOUT[1:6]_DIVIDE Integer 1 to 128 1 Specifies the amount to divide theassociated CLKOUT clock output if adifferent frequency is desired. This numberin combination with the CLKFBOUT_MULTand DIVCLK_DIVIDE values will determinethe output frequency.CLOCK_HOLD Boolean FALSE, TRUE FALSE When TRUE, holds the VCO frequency closeto the frequency prior to losing CLKIN.DIVCLK_DIVIDE Integer 1 to 128 1 Specifies the division ratio for all outputclocks with respect to the input clock.Effectively divides the CLKIN going intothe PFD.REF_JITTER2 3significantdigit Float0.000 to0.9990.010 The reference clock2 jitter is specified interms of the UI which is a percentage ofthe reference clock. The number providedshould be the maximum peak to peak valueour part can expect on the input clock.Default is 0.1UI. This parameter shouldsupport three decimal places.STARTUP_WAIT Boolean FALSE, TRUE FALSE When TRUE, wait for the MMCM(s) thathave this attribute attached to them to lockbefore DONE goes High.VHDL Instantiation Template-- MMCM_ADV: MMCM is a mixed signal block designed to support clock network deskew, frequency synthesis, and jitter reduction.-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2MMCM_ADV_inst : MMCM_ADVgeneric map (BANDWIDTH => "OPTIMIZED",CLKFBOUT_MULT_F => 1.0,CLKFBOUT_PHASE => 0.0,CLKFBOUT_USE_FINE_PS => FALSE,CLKIN1_PERIOD => 0.0,CLKIN2_PERIOD => 0.0,CLKOUT0_DIVIDE_F => 1.0,CLKOUT0_DUTY_CYCLE => 0.5,CLKOUT0_PHASE => 0.0,CLKOUT0_USE_FINE_PS => FALSE,CLKOUT1_DIVIDE => 1,CLKOUT1_DUTY_CYCLE => 0.5,CLKOUT1_PHASE => 0.0,CLKOUT1_USE_FINE_PS => FALSE,CLKOUT2_DIVIDE => 1,CLKOUT2_DUTY_CYCLE => 0.5,-- PLL bandwidth control, sets the MMCM bandwidth. Selecting HIGH sets-- the MMCM programming algorithm to the highest setting possible while-- maintaining good MMCM performance (i.e. low jitter, low jitter-- peaking, maximum phase margin). Selecting LOW sets the MMCM algorithm-- to the lowest setting possible while maintaining good MMCM-- performance. Selecting Optimized allows the MMCM programming-- algorithm to configure the MMCM in the best performance mode without-- trying to reach any particular bandwidth.-- Counter multiply value, Now supports non-integer values-- Only supported when CLKFBOUT_MULT is an integer value-- Counter fine variable phase shift enable, only supported when-- CLKFBOUT_MULT is an integer value-- The reference clock frequency is required for properly configuring-- the LOCK detect circuit and checking to make sure the VCO is-- operating within the allowed range. If no value is specified, a-- warning should be issued stating it was not provided so no error-- checking will be done.-- The reference clock frequency is required for properly configuring-- the LOCK detect circuit and checking to make sure the VCO is-- operating within the allowed range. If no value is specified, a-- warning should be issued stating it was not provided so no error-- checking will be done.-- Counter divide value, Now supports non-integer values but you lose-- CLKOUT5-- Counter output duty cycle-- Counter output phase relative to the output clock, only supported-- when CLKOUT0_DIVIDE is an integer value.-- Counter fine variable phase shift enable.-- Counter divide value-- Counter output duty cycle-- Counter output phase relative to the output clock-- Counter fine variable phase shift enable.-- Counter divide value-- Counter output duty cycleVirtex-6 Libraries Guide for HDL Designs220 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsCLKOUT2_PHASE => 0.0,CLKOUT2_USE_FINE_PS => FALSE,CLKOUT3_DIVIDE => 1,CLKOUT3_DUTY_CYCLE => 0.5,CLKOUT3_PHASE => 0.0,CLKOUT3_USE_FINE_PS => FALSE,CLKOUT4_CASCADE => FALSE,CLKOUT4_DIVIDE => 1,CLKOUT4_DUTY_CYCLE => 0.5,CLKOUT4_PHASE => 0.0,CLKOUT4_USE_FINE_PS => FALSE,CLKOUT5_DIVIDE => 1,CLKOUT5_DUTY_CYCLE => 0.5,CLKOUT5_PHASE => 0.0,CLKOUT5_USE_FINE_PS => FALSE,CLKOUT6_DIVIDE => 1,CLKOUT6_DUTY_CYCLE => 0.5,CLKOUT6_PHASE => 0.0,CLKOUT6_USE_FINE_PS => FALSE,CLOCK_HOLD => FALSE,COMPENSATION => "ZHOLD",DIVCLK_DIVIDE => 1,REF_JITTER1 => 0.0,REF_JITTER2 => 0.0,-- Counter output phase relative to the output clock-- Counter fine variable phase shift enable.-- Counter divide value-- Counter output duty cycle-- Counter output phase relative to the output clock-- Counter fine variable phase shift enable.-- Counter divide value-- Counter output duty cycle-- Counter output phase relative to the output clock-- Counter fine variable phase shift enable.-- Counter divide value-- Counter output duty cycle-- Counter output phase relative to the output clock-- Counter fine variable phase shift enable.-- Counter divide value-- Counter output duty cycle-- Counter output phase relative to the output clock-- Counter fine variable phase shift enable.-- Defines how the PLL feedback is configured. SYSTEM_SYNCHRONOUS-- indicates the MMCM is configured to provide a negative hold time-- SOURCE_SYNCHRONOUS indicates the MMCM is configured to provide a zero-- hold time SYSTEM_SYNCHRONOUS also does the AUTO detect of the-- feedback and it indicates the MMCM is configured based on how a-- customer has connected it. This can be any of the following: INTERNAL-- indicates the MMCM is using its own internal feedback path so no-- delay is being compensated. EXTERNAL indicates a network external to-- the FPGA is being compensated. HROWCLK indicates the path between the-- MMCM and the HROWCLK is being compensated CASCADE indicates cascading-- of 2 MMCM’s.-- Counter divide value, always configured for 50% duty cycle-- The reference clock2 jitter is specified in terms of the UI which is-- a percentage of the reference clock. The number provided should be-- the maximum peak to peak value our part can expect on the input-- clock. Default is 0.1UI. This parameter should support out to three-- decimal places.-- The reference clock1 jitter is specified in terms of the UI which is-- a percentage of the reference clock. The number provided should be-- the maximum peak to peak value our part can expect on the input-- clock. Default is 0.1UI. This parameter should support out to three-- decimal places.-- When TRUE, the MMCM locks before DONE goes highSTARTUP_WAIT => FALSE)port map (CLKFBOUT => CLKFBOUT,-- 1-bit MMCM Feedback clock outputCLKFBOUTB => CLKFBOUTB, -- 1-bit Inverted MMCM feedback clock outputCLKFBSTOPPED => CLKFBSTOPPED, -- 1-bit Status pin indicating that the feedback clock has stopped.CLKINSTOPPED => CLKINSTOPPED, -- 1-bit Status pin indicating that the input clock has stoppedCLKOUT0 => CLKOUT0, -- 1-bit MMCM clock output 0CLKOUT0B => CLKOUT0B, -- 1-bit Inverted MMCM clock output 0CLKOUT1 => CLKOUT1, -- 1-bit MMCM clock output 1CLKOUT1B => CLKOUT1B, -- 1-bit Inverted MMCM clock output 1CLKOUT2 => CLKOUT2, -- 1-bit MMCM clock output 2CLKOUT2B => CLKOUT2B, -- 1-bit Inverted MMCM clock output 2CLKOUT3 => CLKOUT3, -- 1-bit MMCM clock output 3CLKOUT3B => CLKOUT3B, -- 1-bit Inverted MMCM clock output 3CLKOUT4 => CLKOUT4, -- 1-bit MMCM clock output 4CLKOUT5 => CLKOUT5,CLKOUT6 => CLKOUT6,DO => DO,DRDY => DRDY,LOCKED => LOCKED,PSDONE => PSDONE,CLKFBIN => CLKFBIN,CLKIN1 => CLKIN1,CLKIN2 => CLKIN2,CLKINSEL => CLKINSEL,DADDR => DADDR,DCLK => DCLK,DEN => DEN,DI => DI,DWE => DWE,-- 1-bit MMCM clock output 5, not used if CLKOUT0 is not an integer-- 1-bit MMCM clock output 6, not used if CLKFBOUT_MULT is not an integer-- 16-bit DRP output signals-- 1-bit DRP ready signal-- 1-bit MMC locked signal-- 1-bit Phase shift done-- 1-bit Feedback clock pin to the MMCM-- 1-bit Reference clock pin 1 to the MMCM-- 1-bit Reference clock pin 2 to the MMCM-- 1-bit Clock select control pin to the MMCM; 1 = CLKIN1; 0=CLKIN2-- 7-bit DRP address control signals-- 1-bit DRP clock signal (connects to interconnect clock)-- 1-bit DRP enable signal-- 16-bit DRP data inputs-- 1-bit DRP write enableVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 221

Chapter 4: About Design Elements);PSCLK => PSCLK,PSEN => PSEN,PSINCDEC => PSINCDEC,PWRDWN => PWRDWN,RST => RST-- 1-bit Phase shift clock-- 1-bit Phase shift enable-- 1-bit Phase shift Increment/Decrement control-- 1-bit Power down-- 1-bit MMCM global reset pin-- End of MMCM_ADV_inst instantiationVerilog Instantiation Template// MMCM_ADV: MMCM is a mixed signal block designed to support clock network deskew, frequency synthesis, and jitter reduction.// Virtex-6// Xilinx HDL Language Template, version 11.1MMCM_ADV #(.BANDWIDTH("OPTIMIZED"),// PLL bandwidth control, sets the MMCM bandwidth. Selecting HIGH sets// the MMCM programming algorithm to the highest setting possible while// maintaining good MMCM performance (i.e. low jitter, low jitter// peaking, maximum phase margin). Selecting LOW sets the MMCM algorithm// to the lowest setting possible while maintaining good MMCM// performance. Selecting Optimized allows the MMCM programming algorithm// to configure the MMCM in the best performance mode without trying to// reach any particular bandwidth.// Counter multiply value, Now supports non-integer values// Only supported when CLKFBOUT_MULT is an integer value.CLKFBOUT_MULT_F(1.0),.CLKFBOUT_PHASE(0.0),.CLKFBOUT_USE_FINE_PS("FALSE"), // Counter fine variable phase shift enable, only supported when// CLKFBOUT_MULT is an integer value.CLKIN1_PERIOD(0.0),// The reference clock frequency is required for properly configuring the// LOCK detect circuit and checking to make sure the VCO is operating// within the allowed range. If no value is specified, a warning should// be issued stating it was not provided so no error checking will be// done..CLKIN2_PERIOD(0.0),.CLKOUT0_DIVIDE_F(1.0),.CLKOUT0_DUTY_CYCLE(0.5),.CLKOUT0_PHASE(0.0),.CLKOUT0_USE_FINE_PS("FALSE"),.CLKOUT1_DIVIDE(1),.CLKOUT1_DUTY_CYCLE(0.5),.CLKOUT1_PHASE(0.0),.CLKOUT1_USE_FINE_PS("FALSE"),.CLKOUT2_DIVIDE(1),.CLKOUT2_DUTY_CYCLE(0.5),.CLKOUT2_PHASE(0.0),.CLKOUT2_USE_FINE_PS("FALSE"),.CLKOUT3_DIVIDE(1),.CLKOUT3_DUTY_CYCLE(0.5),.CLKOUT3_PHASE(0.0),.CLKOUT3_USE_FINE_PS("FALSE"),.CLKOUT4_CASCADE("FALSE"),.CLKOUT4_DIVIDE(1),.CLKOUT4_DUTY_CYCLE(0.5),.CLKOUT4_PHASE(0.0),.CLKOUT4_USE_FINE_PS("FALSE"),.CLKOUT5_DIVIDE(1),.CLKOUT5_DUTY_CYCLE(0.5),.CLKOUT5_PHASE(0.0),.CLKOUT5_USE_FINE_PS("FALSE"),.CLKOUT6_DIVIDE(1),.CLKOUT6_DUTY_CYCLE(0.5),.CLKOUT6_PHASE(0.0),.CLKOUT6_USE_FINE_PS("FALSE"),.CLOCK_HOLD("FALSE"),.COMPENSATION("ZHOLD"),// The reference clock frequency is required for properly configuring the// LOCK detect circuit and checking to make sure the VCO is operating// within the allowed range. If no value is specified, a warning should// be issued stating it was not provided so no error checking will be// done.// Counter divide value, Now supports non-integer values but you lose// CLKOUT5// Counter output duty cycle// Counter output phase relative to the output clock, only supported when// CLKOUT0_DIVIDE is an integer value.// Counter fine variable phase shift enable.// Counter divide value// Counter output duty cycle// Counter output phase relative to the output clock// Counter fine variable phase shift enable.// Counter divide value// Counter output duty cycle// Counter output phase relative to the output clock// Counter fine variable phase shift enable.// Counter divide value// Counter output duty cycle// Counter output phase relative to the output clock// Counter fine variable phase shift enable.// Counter divide value// Counter output duty cycle// Counter output phase relative to the output clock// Counter fine variable phase shift enable.// Counter divide value// Counter output duty cycle// Counter output phase relative to the output clock// Counter fine variable phase shift enable.// Counter divide value// Counter output duty cycle// Counter output phase relative to the output clock// Counter fine variable phase shift enable.// Defines how the PLL feedback is configured. SYSTEM_SYNCHRONOUS// indicates the MMCM is configured to provide a negative hold timeVirtex-6 Libraries Guide for HDL Designs222 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design Elements.DIVCLK_DIVIDE(1),.REF_JITTER1(0.0),.REF_JITTER2(0.0),// SOURCE_SYNCHRONOUS indicates the MMCM is configured to provide a zero// hold time SYSTEM_SYNCHRONOUS also does the AUTO detect of the feedback// and it indicates the MMCM is configured based on how a customer has// connected it. This can be any of the following: INTERNAL indicates the// MMCM is using its own internal feedback path so no delay is being// compensated. EXTERNAL indicates a network external to the FPGA is// being compensated. HROWCLK indicates the path between the MMCM and the// HROWCLK is being compensated CASCADE indicates cascading of 2 MMCM’s.// Counter divide value, always configured for 50% duty cycle// The reference clock2 jitter is specified in terms of the UI which is a// percentage of the reference clock. The number provided should be the// maximum peak to peak value our part can expect on the input clock.// Default is 0.1UI. This parameter should support out to three decimal// places.// The reference clock1 jitter is specified in terms of the UI which is a// percentage of the reference clock. The number provided should be the// maximum peak to peak value our part can expect on the input clock.// Default is 0.1UI. This parameter should support out to three decimal// places.// When TRUE, the MMCM locks before DONE goes high.STARTUP_WAIT("FALSE"))MMCM_ADV_inst (.CLKFBOUT(CLKFBOUT),// 1-bit MMCM Feedback clock output.CLKFBOUTB(CLKFBOUTB), // 1-bit Inverted MMCM feedback clock output.CLKFBSTOPPED(CLKFBSTOPPED), // 1-bit Status pin indicating that the feedback clock has stopped..CLKINSTOPPED(CLKINSTOPPED), // 1-bit Status pin indicating that the input clock has stopped.CLKOUT0(CLKOUT0), // 1-bit MMCM clock output 0.CLKOUT0B(CLKOUT0B), // 1-bit Inverted MMCM clock output 0.CLKOUT1(CLKOUT1), // 1-bit MMCM clock output 1.CLKOUT1B(CLKOUT1B), // 1-bit Inverted MMCM clock output 1.CLKOUT2(CLKOUT2), // 1-bit MMCM clock output 2.CLKOUT2B(CLKOUT2B), // 1-bit Inverted MMCM clock output 2.CLKOUT3(CLKOUT3), // 1-bit MMCM clock output 3.CLKOUT3B(CLKOUT3B), // 1-bit Inverted MMCM clock output 3.CLKOUT4(CLKOUT4), // 1-bit MMCM clock output 4.CLKOUT5(CLKOUT5),.CLKOUT6(CLKOUT6),.DO(DO),.DRDY(DRDY),.LOCKED(LOCKED),.PSDONE(PSDONE),.CLKFBIN(CLKFBIN),.CLKIN1(CLKIN1),.CLKIN2(CLKIN2),.CLKINSEL(CLKINSEL),.DADDR(DADDR),.DCLK(DCLK),.DEN(DEN),.DI(DI),.DWE(DWE),.PSCLK(PSCLK),.PSEN(PSEN),.PSINCDEC(PSINCDEC),.PWRDWN(PWRDWN),.RST(RST));// End of MMCM_ADV_inst instantiation// 1-bit MMCM clock output 5, not used if CLKOUT0 is not an integer// 1-bit MMCM clock output 6, not used if CLKFBOUT_MULT is not an integer// 16-bit DRP output signals// 1-bit DRP ready signal// 1-bit MMC locked signal// 1-bit Phase shift done// 1-bit Feedback clock pin to the MMCM// 1-bit Reference clock pin 1 to the MMCM// 1-bit Reference clock pin 2 to the MMCM// 1-bit Clock select control pin to the MMCM; 1 = CLKIN1; 0=CLKIN2// 7-bit DRP address control signals// 1-bit DRP clock signal (connects to interconnect clock)// 1-bit DRP enable signal// 16-bit DRP data inputs// 1-bit DRP write enable// 1-bit Phase shift clock// 1-bit Phase shift enable// 1-bit Phase shift Increment/Decrement control// 1-bit Power down// 1-bit MMCM global reset pinFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 223

Chapter 4: About Design ElementsMMCM_BASEConvenience Primitive: Mixed signal block designed to support clock network deskew, frequencysynthesis, and jitter reduction.IntroductionThis component is a mixed signal block designed to support clock network deskew, frequency synthesis,and jitter reduction. The seven "O" counters can be independently programmed which means O0 could beprogrammed to do a divide by 2 while O1 is programmed to do a divide by 3. The only constraint is that theVCO operating frequency must be the same for all the output counters since a single VCO drives all the counters.The CLKFBOUT and CLKFBOUTB pins can be used to drive logic but it must be equal to the CLKin frequency.Port DescriptionsPort Type Width FunctionCLKFBIN Input 1 Feedback clock input.CLKFBOUT Output 1 Dedicated MMCM feedback output.CLKFBOUTB Output 1 Inverted MMCM feedback clock output.CLKIN1 Input 1 General clock input.CLKOUT[0:6] Output 7, 1–bit User configurable clock outputs (0 through 6) that can be dividedversions of the VCO phase outputs (user controllable) from 1(bypassed) to 128. The output clocks are phase aligned to eachother (unless phase shifted) and aligned to the input clock with aproper feedback configuration.CLKOUT[0:3]B Output 4, 1–bit Inverted CLKOUT[0:3].LOCKED Output 1 An output from the MMCM that indicates when the MMCMhas achieved phase alignment within a predefined window andfrequency matching within a predefined PPM range. The MMCMVirtex-6 Libraries Guide for HDL Designs224 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPort Type Width Functionautomatically locks after power on. No extra reset is required.LOCKED will be deasserted if the input clock stops or the phasealignment is violated (e.g., input clock phase shift). The MMCMautomatically reacquires lock after LOCKED is deasserted.PWRDWN Input 1 Powers down instantiated but unused MMCMs.RST Input 1 Asynchronous reset signal. The RST signal is an asynchronousreset for the MMCM. The MMCM will synchronously re-enableitself when this signal is released (i.e., MMCM re-enabled). Areset is not required when the input clock conditions change (e.g.,frequency).Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoRecommendedNoAvailable AttributesAttribute Type Allowed Values Default DescriptionBANDWIDTH String “OPTIMIZED”,“HIGH”,“LOW”CLKFBOUT_MULT_FCLKFBOUT_PHASE3 significantdigit Float3 significantdigit Float1.000 to64.000-360.000 to360.000CLKIN1_PERIOD Float (nS) 1.000 to1000.000CLKOUT0_DIVIDE_FCLKOUT[0:6]_DUTY_CYCLE3 significantdigit Float3 significantdigit Float1.000 to128.0000.001 to0.999“OPTIMIZED” Specifies the MMCM programmingalgorithm affecting the jitter, phase margin,and other characteristics of the MMCM.1.000 Specifies the amount to multiplyall CLKOUT clock outputs if adifferent frequency is desired. Thisnumber, in combination with theassociated CLKOUT#_DIVIDE value andDIVCLK_DIVIDE value, will determine theoutput frequency.0.000 Specifies the phase offset in degrees ofthe clock feedback output. Shifting thefeedback clock results in a negative phaseshift of all output clocks to the MMCM.0.000 Specifies the input period in ns to theMMCM CLKIN1 input. Resolution is downto the ps. This information is mandatoryand must be supplied.1.000 Specifies the amount to divide theassociated CLKOUT clock output if adifferent frequency is desired. This numberin combination with the CLKFBOUT_MULTand DIVCLK_DIVIDE values will determinethe output frequency.0.500 Specifies the Duty Cycle of the associatedCLKOUT clock output in percentage (i.e.,0.50 will generate a 50% duty cycle).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 225

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionCLKOUT[0:6]_PHASE3 significantdigit Float-360.000 to360.0000.000 Allows specification of the output phaserelationship of the associated CLKOUTclock output in number of degrees offset(i.e., 90 indicates a 90° or ¼ cycle offsetphase offset while 180 indicates a 180° offsetor ½ cycle phase offset).CLOCK_HOLD Boolean FALSE, TRUE FALSE When TRUE, holds the VCO frequency closeto the frequency prior to losing CLKIN.DIVCLK_DIVIDE Integer 1 to 128 1 Specifies the division ratio for all outputclocks with respect to the input clock.Effectively divides the CLKIN going intothe PFD.REF_JITTER13 significantdigit Float0.000 to0.9990.010 Allows specification of the expectedjitter on the reference clock in order tobetter optimize MMCM performance. Abandwidth setting of OPTIMIZED willattempt to choose the best parameter forinput clocking when unknown. If known,then the value provided should be specifiedin terms of the UI percentage (the maximumpeak to peak value) of the expected jitter onthe input clock.STARTUP_WAIT Boolean FALSE, TRUE FALSE When TRUE, wait for the MMCM(s) thathave this attribute attached to them to lockbefore DONE goes High.VHDL Instantiation Template-- MMCM_BASE: MMCM is a mixed signal block designed to support clock network deskew, frequency synthesis, and jitter reduction.-- Virtex-6-- Xilinx HDL Language Template, version 11.1MMCM_BASE_inst : MMCM_BASEgeneric map (BANDWIDTH => "OPTIMIZED",CLKFBOUT_MULT_F => 1.0,CLKFBOUT_PHASE => 0.0,CLKIN1_PERIOD => 0.0,CLKOUT0_DIVIDE_F => 1.0,CLKOUT0_DUTY_CYCLE => 0.5,CLKOUT0_PHASE => 0.0,CLKOUT1_DIVIDE => 1,CLKOUT1_DUTY_CYCLE => 0.5,-- PLL bandwidth control, sets the MMCM bandwidth. Selecting HIGH sets the-- MMCM programming algorithm to the highest setting possible while-- maintaining good MMCM performance (i.e. low jitter, low jitter peaking,-- maximum phase margin). Selecting LOW sets the MMCM algorithm to the lowest-- setting possible while maintaining good MMCM performance. Selecting-- Optimized allows the MMCM programming algorithm to configure the MMCM in-- the best performance mode without trying to reach any particular-- bandwidth.-- Counter multiply value, Now supports non-integer values-- Only supported when CLKFBOUT_MULT is an integer value-- The reference clock frequency is required for properly configuring the-- LOCK detect circuit and checking to make sure the VCO is operating within-- the allowed range. If no value is specified, a warning should be issued-- stating it was not provided so no error checking will be done.-- Counter divide value, Now supports non-integer values but you lose CLKOUT5-- Counter output duty cycle-- Counter output phase relative to the output clock, only supported when-- CLKOUT0_DIVIDE is an integer value.-- Counter divide value-- Counter output duty cycleVirtex-6 Libraries Guide for HDL Designs226 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsCLKOUT1_PHASE => 0.0, -- Counter output phase relative to the output clockCLKOUT2_DIVIDE => 1, -- Counter divide valueCLKOUT2_DUTY_CYCLE => 0.5, -- Counter output duty cycleCLKOUT2_PHASE => 0.0, -- Counter output phase relative to the output clockCLKOUT3_DIVIDE => 1, -- Counter divide valueCLKOUT3_DUTY_CYCLE => 0.5, -- Counter output duty cycleCLKOUT3_PHASE => 0.0, -- Counter output phase relative to the output clockCLKOUT4_CASCADE => FALSE,CLKOUT4_DIVIDE => 1, -- Counter divide valueCLKOUT4_DUTY_CYCLE => 0.5, -- Counter output duty cycleCLKOUT4_PHASE => 0.0, -- Counter output phase relative to the output clockCLKOUT5_DIVIDE => 1, -- Counter divide valueCLKOUT5_DUTY_CYCLE => 0.5, -- Counter output duty cycleCLKOUT5_PHASE => 0.0, -- Counter output phase relative to the output clockCLKOUT6_DIVIDE => 1, -- Counter divide valueCLKOUT6_DUTY_CYCLE => 0.5, -- Counter output duty cycleCLKOUT6_PHASE => 0.0, -- Counter output phase relative to the output clockCLOCK_HOLD => FALSE,DIVCLK_DIVIDE => 1,-- Counter divide value, always configured for 50% duty cycleREF_JITTER1 => 0.0,-- The reference clock2 jitter is specified in terms of the UI which is a-- percentage of the reference clock. The number provided should be the-- maximum peak to peak value our part can expect on the input clock. Default-- is 0.1UI. This parameter should support out to three decimal places.STARTUP_WAIT => FALSE -- When TRUE, the MMCM locks before DONE goes high)port map (CLKFBOUT => CLKFBOUT, -- 1-bit MMCM Feedback clock outputCLKFBOUTB => CLKFBOUTB, -- 1-bit Inverted MMCM feedback clock outputCLKOUT0 => CLKOUT0, -- 1-bit MMCM clock output 0CLKOUT0B => CLKOUT0B, -- 1-bit Inverted MMCM clock output 0CLKOUT1 => CLKOUT1, -- 1-bit MMCM clock output 1CLKOUT1B => CLKOUT1B, -- 1-bit Inverted MMCM clock output 1CLKOUT2 => CLKOUT2, -- 1-bit MMCM clock output 2CLKOUT2B => CLKOUT2B, -- 1-bit Inverted MMCM clock output 2CLKOUT3 => CLKOUT3, -- 1-bit MMCM clock output 3CLKOUT3B => CLKOUT3B, -- 1-bit Inverted MMCM clock output 3CLKOUT4 => CLKOUT4, -- 1-bit MMCM clock output 4CLKOUT5 => CLKOUT5, -- 1-bit MMCM clock output 5, not used if CLKOUT0 is not an integerCLKOUT6 => CLKOUT6, -- 1-bit MMCM clock output 6, not used if CLKFBOUT_MULT is not an integerLOCKED => LOCKED, -- 1-bit MMC locked signalCLKFBIN => CLKFBIN, -- 1-bit Feedback clock pin to the MMCMCLKIN1 => CLKIN1, -- 1-bit Reference clock pin 1 to the MMCMPWRDWN => PWRDWN, -- 1-bit Power downRST => RST-- 1-bit MMCM global reset pin);-- End of MMCM_BASE_inst instantiationVerilog Instantiation Template// MMCM_BASE: MMCM is a mixed signal block designed to support clock network deskew, frequency synthesis, and jitter reduction.// Virtex-6// Xilinx HDL Language Template, version 11.1MMCM_BASE #(.BANDWIDTH("OPTIMIZED"), // PLL bandwidth control, sets the MMCM bandwidth. Selecting HIGH sets the// MMCM programming algorithm to the highest setting possible while// maintaining good MMCM performance (i.e. low jitter, low jitter peaking,// maximum phase margin). Selecting LOW sets the MMCM algorithm to the lowest// setting possible while maintaining good MMCM performance. Selecting// Optimized allows the MMCM programming algorithm to configure the MMCM in// the best performance mode without trying to reach any particular bandwidth..CLKFBOUT_MULT_F(1.0), // Counter multiply value, Now supports non-integer values.CLKFBOUT_PHASE(0.0), // Only supported when CLKFBOUT_MULT is an integer value.CLKIN1_PERIOD(0.0), // The reference clock frequency is required for properly configuring the LOCK// detect circuit and checking to make sure the VCO is operating within the// allowed range. If no value is specified, a warning should be issued stating// it was not provided so no error checking will be done..CLKOUT0_DIVIDE_F(1.0), // Counter divide value, Now supports non-integer values but you lose CLKOUT5.CLKOUT0_DUTY_CYCLE(0.5),.CLKOUT0_PHASE(0.0),// Counter output duty cycle// Counter output phase relative to the output clock, only supported when// CLKOUT0_DIVIDE is an integer value.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 227

Chapter 4: About Design Elements.CLKOUT1_DIVIDE(1), // Counter divide value.CLKOUT1_DUTY_CYCLE(0.5), // Counter output duty cycle.CLKOUT1_PHASE(0.0), // Counter output phase relative to the output clock.CLKOUT2_DIVIDE(1), // Counter divide value.CLKOUT2_DUTY_CYCLE(0.5), // Counter output duty cycle.CLKOUT2_PHASE(0.0), // Counter output phase relative to the output clock.CLKOUT3_DIVIDE(1), // Counter divide value.CLKOUT3_DUTY_CYCLE(0.5), // Counter output duty cycle.CLKOUT3_PHASE(0.0), // Counter output phase relative to the output clock.CLKOUT4_CASCADE("FALSE"),.CLKOUT4_DIVIDE(1), // Counter divide value.CLKOUT4_DUTY_CYCLE(0.5), // Counter output duty cycle.CLKOUT4_PHASE(0.0), // Counter output phase relative to the output clock.CLKOUT5_DIVIDE(1), // Counter divide value.CLKOUT5_DUTY_CYCLE(0.5), // Counter output duty cycle.CLKOUT5_PHASE(0.0), // Counter output phase relative to the output clock.CLKOUT6_DIVIDE(1), // Counter divide value.CLKOUT6_DUTY_CYCLE(0.5), // Counter output duty cycle.CLKOUT6_PHASE(0.0), // Counter output phase relative to the output clock.CLOCK_HOLD("FALSE"),.DIVCLK_DIVIDE(1),// Counter divide value, always configured for 50% duty cycle.REF_JITTER1(0.0),// The reference clock2 jitter is specified in terms of the UI which is a// percentage of the reference clock. The number provided should be the// maximum peak to peak value our part can expect on the input clock. Default// is 0.1UI. This parameter should support out to three decimal places..STARTUP_WAIT("FALSE") // When TRUE, the MMCM locks before DONE goes high)MMCM_BASE_inst (.CLKFBOUT(CLKFBOUT), // 1-bit MMCM Feedback clock output.CLKFBOUTB(CLKFBOUTB), // 1-bit Inverted MMCM feedback clock output.CLKOUT0(CLKOUT0), // 1-bit MMCM clock output 0.CLKOUT0B(CLKOUT0B), // 1-bit Inverted MMCM clock output 0.CLKOUT1(CLKOUT1), // 1-bit MMCM clock output 1.CLKOUT1B(CLKOUT1B), // 1-bit Inverted MMCM clock output 1.CLKOUT2(CLKOUT2), // 1-bit MMCM clock output 2.CLKOUT2B(CLKOUT2B), // 1-bit Inverted MMCM clock output 2.CLKOUT3(CLKOUT3), // 1-bit MMCM clock output 3.CLKOUT3B(CLKOUT3B), // 1-bit Inverted MMCM clock output 3.CLKOUT4(CLKOUT4), // 1-bit MMCM clock output 4.CLKOUT5(CLKOUT5), // 1-bit MMCM clock output 5, not used if CLKOUT0 is not an integer.CLKOUT6(CLKOUT6), // 1-bit MMCM clock output 6, not used if CLKFBOUT_MULT is not an integer.LOCKED(LOCKED), // 1-bit MMC locked signal.CLKFBIN(CLKFBIN), // 1-bit Feedback clock pin to the MMCM.CLKIN1(CLKIN1), // 1-bit Reference clock pin 1 to the MMCM.PWRDWN(PWRDWN), // 1-bit Power down.RST(RST)// 1-bit MMCM global reset pin);// End of MMCM_BASE_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs228 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsMUXF7Primitive: 2-to-1 Look-Up Table Multiplexer with General OutputIntroductionThis design element provides a multiplexer function for use in creating a function-of-7 look-up table or an 8-to-1multiplexer in combination with the associated look-up tables. Local outputs (LO) of MUXF6 are connectedto the I0 and I1 inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects I0.When High, S selects I1.The variants, “MUXF7_D” and “MUXF7_L”, provide additional types of outputs that can be used by differenttiming models for more accurate pre-layout timing estimation.Logic TableInputsOutputsS I0 I1 O0 I0 X I01 X I1 I1X 0 0 0X 1 1 1Port DescriptionsPort Direction Width FunctionO Output 1 Output of MUX to general routingI0 Input 1 Input (tie to MUXF6 LO out)I1 Input 1 Input (tie to MUXF6 LO out)S Input 1 Input select to MUXDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 229

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- MUXF7: CLB MUX to tie two MUXF6’s together with general output-- For use with all FPGAs-- Xilinx HDL Libraries Guide, version 11.2MUXF7_inst : MUXF7port map (O => O, -- Output of MUX to general routingI0 => I0, -- Input (tie to MUXF6 LO out or LUT6 O6 pin)I1 => I1, -- Input (tie to MUXF6 LO out or LUT6 O6 pin)S => S -- Input select to MUX);-- End of MUXF7_inst instantiationVerilog Instantiation Template// MUXF7: CLB MUX to tie two LUT6’s or MUXF6’s together with general output// For use with all FPGAs// Xilinx HDL Libraries Guide, version 11.2MUXF7 MUXF7_inst (.O(O), // Output of MUX to general routing.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin).I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin).S(S) // Input select to MUX);// End of MUXF7_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs230 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsMUXF7_DPrimitive: 2-to-1 Look-Up Table Multiplexer with Dual OutputIntroductionThis design element provides a multiplexer function for use in creating a function-of-7 look-up table or a 16-to-1multiplexer in combination with the associated look-up tables. Local outputs (LO) of MUXF6 are connectedto the I0 and I1 inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects I0.When High, S selects I1.Outputs O and LO are functionally identical. The O output is a general interconnect. The LO output connects toother inputs in the same CLB slice.Logic TableInputsOutputsS I0 I1 O LO0 I0 X I0 I01 X I1 I1 I1X 0 0 0 0X 1 1 1 1Port DescriptionsPort Direction Width FunctionO Output 1 Output of MUX to general routingLO Output 1 Output of MUX to local routingI0 Input 1 Input (tie to MUXF6 LO out)I1 Input 1 Input (tie to MUXF6 LO out)S Input 1 Input select to MUXDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 231

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- MUXF7_D: CLB MUX to tie two MUXF6’s together with general and local outputs-- For use with all FPGAs-- Xilinx HDL Libraries Guide, version 11.2MUXF7_D_inst : MUXF7_Dport map (LO => LO, -- Ouptut of MUX to local routingO => O, -- Output of MUX to general routingI0 => I0, -- Input (tie to MUXF6 LO out or LUT6 O6 pin)I1 => I1, -- Input (tie to MUXF6 LO out or LUT6 O6 pin)S => S -- Input select to MUX);-- End of MUXF7_D_inst instantiationVerilog Instantiation Template// MUXF7_D: CLB MUX to tie two LUT6’s or MUXF6’s together with general and local outputs// For use with all FPGAs// Xilinx HDL Libraries Guide, version 11.2MUXF7_D MUXF7_D_inst (.LO(LO), // Ouptut of MUX to local routing.O(O), // Output of MUX to general routing.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin).I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin).S(S) // Input select to MUX);// End of MUXF7_D_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs232 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsMUXF7_LPrimitive: 2-to-1 look-up table Multiplexer with Local OutputIntroductionThis design element provides a multiplexer function for use in creating a function-of-7 look-up table or a 16-to-1multiplexer in combination with the associated look-up tables. Local outputs (LO) of MUXF6 are connectedto the I0 and I1 inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects I0.When High, S selects I1.The LO output connects to other inputs in the same CLB slice.Logic TableInputsOutputS I0 I1 LO0 I0 X I01 X I1 I1X 0 0 0X 1 1 1Port DescriptionsPort Direction Width FunctionLO Output 1 Output of MUX to local routingI0 Input 1 InputI1 Input 1 InputS Input 1 Input select to MUXDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 233

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- MUXF7_L: CLB MUX to tie two MUXF6’s together with local output-- For use with all FPGAs-- Xilinx HDL Libraries Guide, version 11.2MUXF7_L_inst : MUXF7_Lport map (LO => LO, -- Output of MUX to local routingI0 => I0, -- Input (tie to MUXF6 LO out or LUT6 O6 pin)I1 => I1, -- Input (tie to MUXF6 LO out or LUT6 O6 pin)S => S -- Input select to MUX);-- End of MUXF7_L_inst instantiationVerilog Instantiation Template// MUXF7_L: CLB MUX to tie two LUT6’s or MUXF6’s together with local output// For use with all FPGAs// Xilinx HDL Libraries Guide, version 11.2MUXF7_L MUXF7_L_inst (.LO(LO), // Output of MUX to local routing.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin).I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin).S(S) // Input select to MUX);// End of MUXF7_L_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs234 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsMUXF8Primitive: 2-to-1 Look-Up Table Multiplexer with General OutputIntroductionThis design element provides a multiplexer function in eight slices for creating a function-of-8 look-up table or a16-to-1 multiplexer in combination with the associated look-up tables, MUXF5s, MUXF6s, and MUXF7s. Localoutputs (LO) of MUXF7 are connected to the I0 and I1 inputs of the MUXF8. The S input is driven from anyinternal net. When Low, S selects I0. When High, S selects I1.Logic TableInputsOutputsS I0 I1 O0 I0 X I01 X I1 I1X 0 0 0X 1 1 1Port DescriptionsPort Direction Width FunctionO Output 1 Output of MUX to general routingI0 Input 1 Input (tie to MUXF7 LO out)I1 Input 1 Input (tie to MUXF7 LO out)S Input 1 Input select to MUXDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 235

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- MUXF8: CLB MUX to tie two MUXF7’s together with general output-- For use with all FPGAs-- Xilinx HDL Libraries Guide, version 11.2MUXF8_inst : MUXF8port map (O => O, -- Output of MUX to general routingI0 => I0, -- Input (tie to MUXF7 LO out)I1 => I1, -- Input (tie to MUXF7 LO out)S => S -- Input select to MUX);-- End of MUXF8_inst instantiationVerilog Instantiation Template// MUXF8: CLB MUX to tie two MUXF7’s together with general output// For use with all FPGAs// Xilinx HDL Libraries Guide, version 11.2MUXF8 MUXF8_inst (.O(O), // Output of MUX to general routing.I0(I0), // Input (tie to MUXF7 LO out).I1(I1), // Input (tie to MUXF7 LO out).S(S) // Input select to MUX);// End of MUXF8_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs236 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsMUXF8_DPrimitive: 2-to-1 Look-Up Table Multiplexer with Dual OutputIntroductionThis design element provides a multiplexer function in eight slices for creating a function-of-8 look-up table or a32-to-1 multiplexer in combination with the associated four look-up tables and two MUXF8s. Local outputs(LO) of MUXF7 are connected to the I0 and I1 inputs of the MUXF8. The S input is driven from any internalnet. When Low, S selects I0. When High, S selects I1.Outputs O and LO are functionally identical. The O output is a general interconnect. The LO output connects toother inputs in the same CLB slice.Logic TableInputsOutputsS I0 I1 O LO0 I0 X I0 I01 X I1 I1 I1X 0 0 0 0X 1 1 1 1Port DescriptionsPort Direction Width FunctionO Output 1 Output of MUX to general routingLO Output 1 Output of MUX to local routingI0 Input 1 Input (tie to MUXF7 LO out)I1 Input 1 Input (tie to MUXF7 LO out)S Input 1 Input select to MUXDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 237

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- MUXF8_D: CLB MUX to tie two MUXF7’s together with general and local outputs-- For use with all FPGAs-- Xilinx HDL Libraries Guide, version 11.2MUXF8_D_inst : MUXF8_Dport map (LO => LO, -- Ouptut of MUX to local routingO => O, -- Output of MUX to general routingI0 => I0, -- Input (tie to MUXF7 LO out)I1 => I1, -- Input (tie to MUXF7 LO out)S => S -- Input select to MUX);-- End of MUXF8_D_inst instantiationVerilog Instantiation Template// MUXF8_D: CLB MUX to tie two MUXF7’s together with general and local outputs// For use with all FPGAs// Xilinx HDL Libraries Guide, version 11.2MUXF8_D MUXF8_D_inst (.LO(LO), // Ouptut of MUX to local routing.O(O), // Output of MUX to general routing.I0(I0), // Input (tie to MUXF7 LO out).I1(I1), // Input (tie to MUXF7 LO out).S(S) // Input select to MUX);// End of MUXF8_D_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs238 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsMUXF8_LPrimitive: 2-to-1 Look-Up Table Multiplexer with Local OutputIntroductionThis design element provides a multiplexer function in eight slices for creating a function-of-8 look-up table or a32-to-1 multiplexer in combination with the associated four look-up tables and two MUXF8s. Local outputs(LO) of MUXF7 are connected to the I0 and I1 inputs of the MUXF8. The S input is driven from any internalnet. When Low, S selects I0. When High, S selects I1.The LO output connects to other inputs in the same CLB slice.Logic TableInputsOutputS I0 I1 LO0 I0 X I01 X I1 I1X 0 0 0X 1 1 1Port DescriptionsPort Direction Width FunctionLO Output 1 Output of MUX to local routingI0 Input 1 Input (tie to MUXF7 LO out)I1 Input 1 Input (tie to MUXF7 LO out)S Input 1 Input select to MUXDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 239

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- MUXF8_L: CLB MUX to tie two MUXF7’s together with local output-- For use with all FPGAs-- Xilinx HDL Libraries Guide, version 11.2MUXF8_L_inst : MUXF8_Lport map (LO => LO, -- Output of MUX to local routingI0 => I0, -- Input (tie to MUXF7 LO out)I1 => I1, -- Input (tie to MUXF7 LO out)S => S -- Input select to MUX);-- End of MUXF8_L_inst instantiationVerilog Instantiation Template// MUXF8_L: CLB MUX to tie two MUXF7’s together with local output// For use with all FPGAs// Xilinx HDL Libraries Guide, version 11.2MUXF8_L MUXF8_L_inst (.LO(LO), // Output of MUX to local routing.I0(I0), // Input (tie to MUXF7 LO out).I1(I1), // Input (tie to MUXF7 LO out).S(S) // Input select to MUX);// End of MUXF8_L_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs240 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsOBUFPrimitive: Output BufferIntroductionThis design element is a simple output buffer used to drive output signals to the FPGA device pins that do notneed to be 3-stated (constantly driven). Either an OBUF, OBUFT, OBUFDS, or OBUFTDS must be connected toevery output port in the design.This element isolates the internal circuit and provides drive current for signals leaving a chip. It exists ininput/output blocks (IOB). Its output (O) is connected to an OPAD or an IOPAD. The interface standard usedby this element is LVTTL. Also, this element has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.Port DescriptionsPort Direction Width FunctionO Output 1 Output of OBUF to be connected directly to top-level outputport.I Input 1 Input of OBUF. Connect to the logic driving the output port.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 241

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- OBUF: Single-ended Output Buffer-- All devices-- Xilinx HDL Libraries Guide, version 11.2OBUF_inst : OBUFgeneric map (DRIVE => 12,IOSTANDARD => "DEFAULT",SLEW => "SLOW")port map (O => O, -- Buffer output (connect directly to top-level port)I => I -- Buffer input);-- End of OBUF_inst instantiationVerilog Instantiation Template// OBUF: Single-ended Output Buffer// All devices// Xilinx HDL Libraries Guide, version 11.2OBUF #(.DRIVE(12), // Specify the output drive strength.IOSTANDARD("DEFAULT"), // Specify the output I/O standard.SLEW("SLOW") // Specify the output slew rate) OBUF_inst (.O(O), // Buffer output (connect directly to top-level port).I(I) // Buffer input);// End of OBUF_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs242 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsOBUFDSPrimitive: Differential Signaling Output BufferIntroductionThis design element is a single output buffer that supports low-voltage, differential signaling (1.8 v CMOS).OBUFDS isolates the internal circuit and provides drive current for signals leaving the chip. Its output isrepresented as two distinct ports (O and OB), one deemed the "master" and the other the "slave." The master andthe slave are opposite phases of the same logical signal (for example, MYNET and MYNETB).Logic TableInputsOutputsI O OB0 0 11 1 0Port DescriptionsPort Direction Width FunctionO Output 1 Diff_p output (connect directly to top level port)OB Output 1 Diff_n output (connect directly to top level port)I Input 1 Buffer inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 243

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- OBUFDS: Differential Output Buffer-- Spartan-3/3E/3A-- Xilinx HDL Libraries Guide, version 11.2OBUFDS_inst : OBUFDSgeneric map (IOSTANDARD => "DEFAULT")port map (O => O, -- Diff_p output (connect directly to top-level port)OB => OB, -- Diff_n output (connect directly to top-level port)I => I -- Buffer input);-- End of OBUFDS_inst instantiationVerilog Instantiation Template// OBUFDS: Differential Output Buffer// Virtex-4/5, Spartan-3/3E/3A// Xilinx HDL Libraries Guide, version 11.2OBUFDS #(.IOSTANDARD("DEFAULT") // Specify the output I/O standard) OBUFDS_inst (.O(O), // Diff_p output (connect directly to top-level port).OB(OB), // Diff_n output (connect directly to top-level port).I(I) // Buffer input);// End of OBUFDS_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs244 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsOBUFTDSPrimitive: 3-State Output Buffer with Differential Signaling, Active-Low Output EnableIntroductionThis design element is an output buffer that supports low-voltage, differential signaling. For the OBUFTDS,a design level interface signal is represented as two distinct ports (O and OB), one deemed the "master" andthe other the "slave." The master and the slave are opposite phases of the same logical signal (for example,MYNET_P and MYNET_N).Logic TableInputsOutputsI T O OBX 1 Z Z0 0 0 11 0 1 0Port DescriptionsPort Direction Width FunctionO Output 1 Diff_p output (connect directly to top level port)OB Output 1 Diff_n output (connect directly to top level port)I Input 1 Buffer inputT Input 1 3-state enable inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 245

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- OBUFTDS: Differential 3-state Output Buffer-- Spartan-3/3E/3A-- Xilinx HDL Libraries Guide, version 11.2OBUFTDS_inst : OBUFTDSgeneric map (IOSTANDARD => "DEFAULT")port map (O => O, -- Diff_p output (connect directly to top-level port)OB => OB, -- Diff_n output (connect directly to top-level port)I => I, -- Buffer inputT => T -- 3-state enable input);-- End of OBUFTDS_inst instantiationVerilog Instantiation Template// OBUFTDS: Differential 3-state Output Buffer// Virtex-4/5, Spartan-3/3E/3A// Xilinx HDL Libraries Guide, version 11.2OBUFTDS #(.IOSTANDARD("DEFAULT") // Specify the output I/O standard) OBUFTDS_inst (.O(O), // Diff_p output (connect directly to top-level port).OB(OB), // Diff_n output (connect directly to top-level port).I(I), // Buffer input.T(T) // 3-state enable input);// End of OBUFTDS_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs246 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsODDRPrimitive: Dedicated Dual Data Rate (DDR) Output RegisterIntroductionThis design element is a dedicated output register for use in transmitting dual data rate (DDR) signals fromFPGA devices. The ODDR primitive’s interface with the FPGA fabric are not limited to opposite edges. TheODDR is available with modes that allow data to be presented from the FPGA fabric at the same clock edge. Thisfeature allows designers to avoid additional timing complexities and CLB usage. In addition, the ODDR worksin conjunction with SelectIO features.ODDR ModesThis element has two modes of operation. These modes are set by the DDR_CLK_EDGE attribute.• OPPOSITE_EDGE mode - The data transmit interface uses the classic DDR methodology. Given a data andclock at pin D1-2 and C respectively, D1 is sampled at every positive edge of clock C, and D2 is sampled atevery negative edge of clock C. Q changes every clock edge.• SAME_EDGE mode - Data is still transmitted at the output of the ODDR by opposite edges of clock C.However, the two inputs to the ODDR are clocked with a positive clock edge of clock signal C and an extraregister is clocked with a negative clock edge of clock signal C. Using this feature, DDR data can now bepresented into the ODDR at the same clock edge.Port DescriptionsPort Type Width FunctionQ Output 1 Data Output (DDR) - The ODDR output that connects to the IOBpad.C Input 1 Clock Input - The C pin represents the clock input pin.CE Input 1 Clock Enable Input - When asserted High, this port enables theclock input on port C.D1 : D2 Input 1 (each) Data Input - This pin is where the DDR data is presented intothe ODDR module.R Input 1 Reset - Depends on how SRTYPE is set.S Input 1 Set - Active High asynchronous set pin. This pin can also beSynchronous depending on the SRTYPE attribute.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 247

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionDDR_CLK_EDGEString"OPPOSITE_EDGE","SAME_EDGE""OPPOSITE_EDGE"DDR clock mode recovery modeselection.INIT Integer 0, 1 1 Q initialization value.SRTYPE String "SYNC", "ASYNC" "SYNC" Set/Reset type selection.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- ODDR: Output Double Data Rate Output Register with Set, Reset-- and Clock Enable.-- Virtex-4/5-- Xilinx HDL Libraries Guide, version 11.2ODDR_inst : ODDRgeneric map(DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"INIT => ’0’, -- Initial value for Q port (’1’ or ’0’)SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")port map (Q => Q, -- 1-bit DDR outputC => C, -- 1-bit clock inputCE => CE, -- 1-bit clock enable inputD1 => D1, -- 1-bit data input (positive edge)D2 => D2, -- 1-bit data input (negative edge)R => R, -- 1-bit reset inputS => S -- 1-bit set input);-- End of ODDR_inst instantiationVerilog Instantiation Template// ODDR: Output Double Data Rate Output Register with Set, Reset// and Clock Enable.// Virtex-4/5/6// Xilinx HDL Libraries Guide, version 11.2ODDR #(.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE".INIT(1’b0), // Initial value of Q: 1’b0 or 1’b1.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC") ODDR_inst (.Q(Q), // 1-bit DDR output.C(C), // 1-bit clock input.CE(CE), // 1-bit clock enable input.D1(D1), // 1-bit data input (positive edge).D2(D2), // 1-bit data input (negative edge).R(R), // 1-bit reset.S(S) // 1-bit set);// End of ODDR_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs248 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsOR2LPrimitive: Two input OR gate implemented in place of a Slice LatchIntroductionThis element allows the specification of a configurable Slice Latch to take the function of a two input OR gate (seeLogic Table). The use of this element can reduce logic levels and increase logic density of the part by trading offregister/latch resources for logic. Xilinx suggests caution when using this component as it can affect registerpacking and density since specifying one or more e AND2B1L or OR2L components in a Slice disallows the useof the remaining registers and latches.Logic TableInputsOutputsDI SRI O0 0 00 1 11 0 11 1 1Port DescriptionsPort Type Width FunctionO Output 1 Output of the OR gate.DI Input 1 Active high input that is generally connected to sourcing LUT locatedin the same Slice.SRI Input 1 Active low input that is generally source from outside of the Slice.Note To allow more than one AND2B1L or OR2B1L to be packed intoa single Slice, a common signal must be connected to this input.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 249

Chapter 4: About Design ElementsOSERDESE1Primitive: Dedicated IOB Output SerializerIntroductionUse this primitive to easily implement a source synchronous interface. This device helps you by saving logicresources that would otherwise be implemented in the FPGA fabric. It also avoids additional timing complexitiesthat you might encounter when you are designing circuitry in the FPGA fabric. This element contains multipleclock inputs to accommodate various applications, and will work in conjunction with the SelectIO featuresof Xilinx® FPGAs.Port DescriptionsPort Type Width FunctionCLK Input 1 High Speed Clock Input – Use this clock input to drive theparallel-to-serial converters. The possible source for the CLK portis from one of the following clock resources:• Ten global clock lines in a clock region• Four regional clock lines• Four clock capable I/Os (within adjacent clock region)• Fabric (through bypass)CLKB Input 1 High speed clock input.Virtex-6 Libraries Guide for HDL Designs250 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPort Type Width FunctionCLKDIV Input 1 Divided High Speed Clock Input – This clock input is used todrive the parallel-to-serial converter. This clock must be a divideddown version of the clock connected to the CLK port. One of thefollowing clock resources can be used as a source for CLKDIV:• Ten global clock lines in a clock region• Four regional clock linesCLKPERF Input 1 Input for performance path from MMCM.CLKPERFDELAY Input 1 Delayed version of BUFO from IODELAYD1 - D6 Input 1 Parallel Data Inputs - Ports D1 to D6 are the location in which allincoming parallel data enters the OSERDES module. This port isconnected to the FPGA fabric, and can be configured from 2 to 6bits. In the extended width mode, this port can be expanded upto 10 bits.IOCLKGLITCH Output 1 Indicate the occurrence of a glitch on the fast clock; Active High.OCBEXTEND Output 1 Used in DDR3 mode to signal that the output circular buffer(OCB) has extended latency to match the CLK to the CLKPERF orCLKPERFDELAY.OCE Input 1 Parallel to serial converter (data) clock enable. This port is usedto enable the output of the data parallel-to-serial converter whenasserted High.ODV Input 1 Used for DDR3. Set to 1 if the ODELAY values exceeds 180 degreesof the clock period.OFB Output 1 Feedback path for Data OutputOQ Output 1 Data Path Output – This port is the data output of the OSERDESmodule. This port connects the output of the data parallel-to-serialconverter to the data input of the IOB pad. In addition, this outputport can also be configured to bypass all the submodules withinthe OSERDES module.RST Input 1 ResetSHIFTIN1/SHIFTIN2SHIFTOUT1/SHIFTOUT2Input 1 Carry Input for Data Input Expansion. Connect toSHIFTOUT1/SHIFTOUT2 of slave.Output 1 Carry Out for data input expansion. Connect toSHIFTIN1/SHIFTIN2 of master.TCE Input 1 Parallel to serial converter (3-state) clock enable – Used to enablethe output of the 3-state signal parallel-to-serial converter whenasserted High.TFB Output 1 3-State Control Output – This port connects output of the 3-stateparallel-to-serial converter to the control/3–state input of theIODELAY.TQ Output 1 3-State Path Output – This port is the 3-state output of theOSERDES module. This port connects the output of the 3-stateparallel-to-serial converter to the control input of the IOB pad.T1 - T4 Input 1 Parallel 3-State Inputs – Ports T1 to T4 are the location where allparallel 3-state signals enter the OSERDES module. This port isconnected to the FPGA fabric, and can be configured from 1 to 4bits. This feature is not supported in the extended width mode.WC Input 1 Used for DDR3. Resets FIFO counters and changes IODELAYfrom IDELAY to ODELAY.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 251

Chapter 4: About Design ElementsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionDATA_RATE_OQ String “DDR”, “SDR” “DDR” Defines whether the data changes at every clockedge or every positive clock edge with respectto CLK.DATA_RATE_TQ String “DDR”,“BUF”,“SDR”“DDR”Defines whether the 3-state changes at everyclock edge, every positive clock edge, or bufferconfiguration with respect to CLK.DATA_WIDTH Integer 4, 2, 3, 5, 6, 7, 8, 10 4 • If DATA_RATE_OQ = DDR, value is limitedto 4, 6, 8, or 10.• If DATA_RATE_OQ = SDR, value is limitedto 2, 3, 4, 5, 6, 7, or 8.DDR3_DATA Integer 1, 0 1 For DDR3, if the I/O is a DQ or DQS pin, set to 1.If control, address, clock, etc. set to 0.INIT_OQ Binary 1’b0 to 1’b1 1’b0 Defines the initial value of OQ output.INIT_TQ Binary 1’b0 to 1’b1 1’b0 Defines the initial value of TQ output.INTERFACE_TYPE String “DEFAULT”,“MEMORY_DDR3”“DEFAULT”To bypass DDR3 circuitry.ODELAY_USED Integer 0, 1 0 BUFO drives IODELAY for write leveling orBUFO alignment.SERDES_MODE String “MASTER”,“SLAVE”“MASTER”Defines whether the OSERDES module is amaster or slave when width expansion is used.SRVAL_OQ Binary 1’b0 to 1’b1 1’b0 Defines the value of OQ output when reset isinvoked.SRVAL_TQ Binary 1’b0 to 1’b1 1’b0 Defines the value of TQ output when reset isinvoked.TRISTATE_WIDTH Integer 4, 1 4 If DATA_RATE_TQ = DDR, DATA_WIDTH = 4,and DATA_RATE_OQ = DDR, value is limited to1 or 4. For all other settings of DATA_RATE_TQ,DATA_WIDTH, and DATA_RATE_OQ, value islimited to 1.VHDL Instantiation Template-- OSERDESE1: Dedicated IOB Output Serializer-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2OSERDESE1_inst : OSERDESE1generic map (DATA_RATE_OQ => "DDR",DATA_RATE_TQ => "DDR",DATA_WIDTH => 4,-- Defines whether the data changes at every clock edge or every positive-- clock edge with respect to CLK.-- Defines whether the 3-state changes at every clock edge, every positive-- clock edge, or buffer configuration with respect to CLK.-- If DATA_RATE_OQ = DDR, value is limited to 4, 6, 8, or 10. If-- DATA_RATE_OQ = SDR, value is limited to 2, 3, 4, 5, 6, 7, or 8.Virtex-6 Libraries Guide for HDL Designs252 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsDDR3_DATA => 1,-- For DDR3, if the I/O is a DQ or DQS pin, set to 1. If control, address,-- clock, etc. set to 0.INIT_OQ => "0",-- Defines the initial value of OQ output.INIT_TQ => "0",-- Defines the initial value of TQ output.INTERFACE_TYPE => "DEFAULT", -- To bypass DDR3 circuitryODELAY_USED => 0,-- BUFO drives IODELAY for write leveling or BUFO alignment.SERDES_MODE => "MASTER", -- Defines whether the OSERDES module is a master or slave when width-- expansion is used.SRVAL_OQ => "0",-- Defines the value of OQ output when reset is invoked.SRVAL_TQ => "0",-- Defines the value of TQ output when reset is invoked.TRISTATE_WIDTH => 4-- If DATA_RATE_TQ = DDR, DATA_WIDTH = 4, and DATA_RATE_OQ = DDR, value is-- limited to 1 or 4. For all other settings of DATA_RATE_TQ, DATA_WIDTH,-- and DATA_RATE_OQ, value is limited to 1.)port map (OCBEXTEND => OCBEXTEND,OFB => OFB,-- 1-bit Feedback path for Data OutputOQ => OQ,-- 1-bit Data Path Output-- SHIFTOUT1/SHIFTOUT2: 1-bit (each) Carry Out for data input expansion. Connect to SHIFTIN1/2 ofmaster.SHIFTOUT1 => SHIFTOUT1,SHIFTOUT2 => SHIFTOUT2,TFB => TFB,);TQ => TQ,CLK => CLK,-- 1-bit 3-State Path Output-- 1-bit High Speed Clock Input - This clock input is used to drive the-- parallel-to-serial converters. The possible source for the CLK port is-- from one of the following clock resources: - Ten global clock lines in a-- clock region - Four regional clock lines - Four clock capable I/Os-- (within adjacent clock region) - Fabric (through bypass).CLKDIV => CLKDIV,-- 1-bit Divided High Speed Clock InputCLKPERF => CLKPERF,-- 1-bit Input for performance path from PLL.CLKPERFDELAY => CLKPERFDELAY, -- 1-bit Delayed version of BUFO from IODELAY-- D1 - D6: 1-bit (each) 1-bit parallel Data InputD1 => D1,D2 => D2,D3 => D3,D4 => D4,D5 => D5,D6 => D6,OCE => OCE,-- 1-bit Parallel to serial converter (data) clock enableODV => ODV,-- 1-bit Used for DDR3. Set to 1 if the ODELAY values exceeds 180 degrees-- of the clock period.RST => RST,-- SHIFTIN1/SHIFTIN2: 1-bit (each) 1-bit Data Input ExpansionSHIFTIN1 => SHIFTIN1,SHIFTIN2 => SHIFTIN2,-- T1 - T4: 1-bit (each) Parallel 3-State InputsT1 => T1,T2 => T2,T3 => T3,T4 => T4,TCE => TCE,WC => WC-- End of OSERDESE1_inst instantiation-- 1-bit Parallel to serial converter (3-state) clock enable-- 1-bit Used for DDR3. Resets FIFO counters and turns IODELAY from IDELAY-- to ODELAY.Verilog Instantiation Template// OSERDESE1: Dedicated IOB Output Serializer// Virtex-6// Xilinx HDL Language Template, version 11.1OSERDESE1 #(.DATA_RATE_OQ("DDR"),.DATA_RATE_TQ("DDR"),// Defines whether the data changes at every clock edge or every positive// clock edge with respect to CLK.// Defines whether the 3-state changes at every clock edge, every positive// clock edge, or buffer configuration with respect to CLK.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 253

Chapter 4: About Design Elements.DATA_WIDTH(4),// If DATA_RATE_OQ = DDR, value is limited to 4, 6, 8, or 10. If DATA_RATE_OQ// = SDR, value is limited to 2, 3, 4, 5, 6, 7, or 8..DDR3_DATA(1),// For DDR3, if the I/O is a DQ or DQS pin, set to 1. If control, address,// clock, etc. set to 0..INIT_OQ(1’b0),// Defines the initial value of OQ output..INIT_TQ(1’b0),// Defines the initial value of TQ output..INTERFACE_TYPE("DEFAULT"), // To bypass DDR3 circuitry.ODELAY_USED(0),// BUFO drives IODELAY for write leveling or BUFO alignment..SERDES_MODE("MASTER"), // Defines whether the OSERDES module is a master or slave when width// expansion is used..SRVAL_OQ(1’b0),// Defines the value of OQ output when reset is invoked..SRVAL_TQ(1’b0),// Defines the value of TQ output when reset is invoked..TRISTATE_WIDTH(4)// If DATA_RATE_TQ = DDR, DATA_WIDTH = 4, and DATA_RATE_OQ = DDR, value is// limited to 1 or 4. For all other settings of DATA_RATE_TQ, DATA_WIDTH, and// DATA_RATE_OQ, value is limited to 1.)OSERDESE1_inst (.OCBEXTEND(OCBEXTEND),.OFB(OFB),// 1-bit Feedback path for Data Output.OQ(OQ),// 1-bit Data Path Output// SHIFTOUT1/SHIFTOUT2: 1-bit (each) Carry Out for data input expansion. Connect to SHIFTIN1/2 ofter..SHIFTOUT1(SHIFTOUT1),.SHIFTOUT2(SHIFTOUT2),.TFB(TFB),);.TQ(TQ),.CLK(CLK),// 1-bit 3-State Path Output// 1-bit High Speed Clock Input - This clock input is used to drive the// parallel-to-serial converters. The possible source for the CLK port is// from one of the following clock resources: - Ten global clock lines in a// clock region - Four regional clock lines - Four clock capable I/Os// (within adjacent clock region) - Fabric (through bypass)..CLKDIV(CLKDIV),// 1-bit Divided High Speed Clock Input.CLKPERF(CLKPERF),// 1-bit Input for performance path from PLL..CLKPERFDELAY(CLKPERFDELAY), // 1-bit Delayed version of BUFO from IODELAY// D1 - D6: 1-bit (each) 1-bit parallel Data Input.D1(D1),.D2(D2),.D3(D3),.D4(D4),.D5(D5),.D6(D6),.OCE(OCE),// 1-bit Parallel to serial converter (data) clock enable.ODV(ODV),// 1-bit Used for DDR3. Set to 1 if the ODELAY values exceeds 180 degrees of// the clock period..RST(RST),// SHIFTIN1/SHIFTIN2: 1-bit (each) 1-bit Data Input Expansion.SHIFTIN1(SHIFTIN1),.SHIFTIN2(SHIFTIN2),// T1 - T4: 1-bit (each) Parallel 3-State Inputs.T1(T1),.T2(T2),.T3(T3),.T4(T4),.TCE(TCE),.WC(WC)// End of OSERDESE1_inst instantiation// 1-bit Parallel to serial converter (3-state) clock enable// 1-bit Used for DDR3. Resets FIFO counters and turns IODELAY from IDELAY// to ODELAY.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs254 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPCIE_2_0Primitive: PCI Express version 2.0 Compliant.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 255

Chapter 4: About Design ElementsIntroductionThis design element is intended for use in conjunction with other resources located in the FPGA, such as theRocketIO transceivers, block RAMs, and various clocking resources. To implement an Endpoint, Root Port, orcustom PCI EXPRESS® design using PCIe_2_0, designers must use the CORE Generator software tool (part ofthe ISE® Design Suite) to create a LogiCORE IP core for PCI EXPRESS designs. The LogiCORE instantiatesthe PCIE_2_0 software primitive, connects the interfaces to the correct FPGA resources, sets all attributes, andpresents a simple, user-friendly interface.Design Entry MethodTo instantiate this component, use the PCI EXPRESS core or an associated core containing the component. Xilinxdoes not recommend direct instantiation of this component.For More Information• See the Virtex-6 FPGA RocketIO GTP Transceivers User Guide.• See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs256 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPULLDOWNPrimitive: Resistor to GND for Input Pads, Open-Drain, and 3-State OutputsIntroductionThis resistor element is connected to input, output, or bidirectional pads to guarantee a logic Low level fornodes that might float.Port DescriptionsPort Direction Width FunctionO Output 1 Pulldown output (connect directly to top level port)Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- PULLDOWN: I/O Buffer Weak Pull-down-- All FPGA-- Xilinx HDL Libraries Guide, version 11.2PULLDOWN_inst : PULLDOWNport map (O => O -- Pulldown output (connect directly to top-level port));-- End of PULLDOWN_inst instantiationVerilog Instantiation Template// PULLDOWN: I/O Buffer Weak Pull-down// All FPGA// Xilinx HDL Libraries Guide, version 11.2PULLDOWN PULLDOWN_inst (.O(O) // Pulldown output (connect directly to top-level port));// End of PULLDOWN_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 257

Chapter 4: About Design ElementsFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs258 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPULLUPPrimitive: Resistor to VCC for Input PADs, Open-Drain, and 3-State OutputsIntroductionThis design element allows for an input, 3-state output or bi-directional port to be driven to a weak highvalue when not being driven by an internal or external source. This element establishes a High logic level foropen-drain elements and macros when all the drivers are off.Port DescriptionsPort Direction Width FunctionO Output 1 Pullup output (connect directly to top level port)Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- PULLUP: I/O Buffer Weak Pull-up-- All FPGA, CoolRunner-II-- Xilinx HDL Libraries Guide, version 11.2PULLUP_inst : PULLUPport map (O => O -- Pullup output (connect directly to top-level port));-- End of PULLUP_inst instantiationVerilog Instantiation Template// PULLUP: I/O Buffer Weak Pull-up// All FPGA, CoolRunner-II// Xilinx HDL Libraries Guide, version 11.2PULLUP PULLUP_inst (.O(O) // Pullup output (connect directly to top-level port));// End of PULLUP_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 259

Chapter 4: About Design ElementsFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs260 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsRAM128X1DPrimitive: 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)IntroductionThis design element is a 128-bit deep by 1-bit wide random access memory and has a read/write port that writesthe value on the D input data pin when the write enable (WE) is high to the location specified by the A addressbus. This happens shortly after the rising edge of the WCLK and that same value is reflected in the data outputSPO. When WE is low, an asynchronous read is initiated in which the contents of the memory location specifiedby the A address bus is output asynchronously to the SPO output. The read port can perform asynchronousread access of the memory by changing the value of the address bus DPRA, and by outputing that value to theDPO data output.Port DescriptionsPort Direction Width FunctionSPO Output 1 Read/Write port data output addressed by ADPO Output 1 Read port data output addressed by DPRAD Input 1 Write data input addressed by AA Input 7 Read/Write port address busDPRA Input 7 Read port address busWE Input 1 Write EnableWCLK Input 1 Write clock (reads are asynchronous)If instantiated, the following connections should be made to this component:• Tie the WCLK input to the desired clock source, the D input to the data source to be stored and the DPOoutput to an FDCE D input or other appropriate data destination.• Optionally, the SPO output can also be connected to the appropriate data destination or else left unconnected.• The WE clock enable pin should be connected to the proper write enable source in the design.• The 7-bit A bus should be connected to the source for the read/write addressing and the 7-bit DPRA busshould be connected to the appropriate read address connections.• An optional INIT attribute consisting of a 128-bit Hexadecimal value can be specified to indicate the initialcontents of the RAM.If left unspecified, the initial contents default to all zeros.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 261

Chapter 4: About Design ElementsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 128-Bit Value All zeros Specifies the initial contents of theRAM.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- RAM128X1D: 128-deep by 1-wide positive edge write, asynchronous read-- dual-port distributed LUT RAM-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2RAM128X1D_inst : RAM128X1Dgeneric map (INIT => X"00000000000000000000000000000000")port map (DPO => DPO, -- Read/Write port 1-bit ouputSPO => SPO, -- Read port 1-bit outputA => A,-- Read/Write port 7-bit address inputD => D,-- RAM data inputDPRA => DPRA, -- Read port 7-bit address inputWCLK => WCLK, -- Write clock inputWE => WE -- RAM data input);-- End of RAM128X1D_inst instantiationVerilog Instantiation Template// RAM128X1D: 128-deep by 1-wide positive edge write, asynchronous read// dual-port distributed LUT RAM// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2RAM128X1D #(.INIT(128’h00000000000000000000000000000000)) RAM128X1D_inst (.DPO(DPO), // Read port 1-bit output.SPO(SPO), // Read/Write port 1-bit output.A(A), // Read/Write port 7-bit address input.D(D), // RAM data input.DPRA(DPRA), // Read port 7-bit address input.WCLK(WCLK), // Write clock input.WE(WE) // Write enable input);// End of RAM128X1D_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs262 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsRAM256X1SPrimitive: 256-Deep by 1-Wide Random Access Memory (Select RAM)IntroductionThis design element is a 256-bit deep by 1-bit wide random access memory with synchronous write andasynchronous read capability. This RAM is implemented using the LUT resources of the device (also knownas Select RAM), and does not consume any of the block RAM resources of the device. If a synchronous readcapability is preferred, a register can be attached to the output and placed in the same slice as long as thesame clock is used for both the RAM and the register. The RAM256X1S has an active, High write enable, WE,so that when that signal is High, and a rising edge occurs on the WCLK pin, a write is performed recordingthe value of the D input data pin into the memory array. The output O displays the contents of the memorylocation addressed by A, regardless of the WE value. When a write is performed, the output is updated to thenew value shortly after the write completes.Port DescriptionsPort Direction Width FunctionO Output 1 Read/Write port data output addressed by AD Input 1 Write data input addressed by AA Input 8 Read/Write port address busWE Input 1 Write EnableWCLK Input 1 Write clock (reads are asynchronous)Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoIf instantiated, the following connections should be made to this component:• Tie the WCLK input to the desired clock source, the D input to the data source to be stored, and the O outputto an FDCE D input or other appropriate data destination.• The WE clock enable pin should be connected to the proper write enable source in the design.• The 8-bit A bus should be connected to the source for the read/write.• An optional INIT attribute consisting of a 256-bit Hexadecimal value can be specified to indicate the initialcontents of the RAM.If left unspecified, the initial contents default to all zeros.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 263

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 256-Bit Value AllzerosSpecifies the initial contents of the RAM.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read-- single-port distributed LUT RAM-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2RAM256X1S_inst : RAM256X1Sgeneric map (INIT => X"0000000000000000000000000000000000000000000000000000000000000000")port map (O => O, -- Read/Write port 1-bit ouputA => A, -- Read/Write port 8-bit address inputD => D, -- RAM data inputWCLK => WCLK, -- Write clock inputWE => WE -- Write enable input);-- End of RAM256X1S_inst instantiationVerilog Instantiation Template// RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read// single-port distributed LUT RAM// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2RAM256X1S #(.INIT(256’h0000000000000000000000000000000000000000000000000000000000000000)) RAM256X1S_inst (.O(O), // Read/Write port 1-bit output.A(A), // Read/Write port 8-bit address input.WE(WE), // Write enable input.WCLK(WCLK), // Write clock input.D(D) // RAM data input);// End of RAM256X1S_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs264 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsRAM32MPrimitive: 32-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM)IntroductionThis design element is a 32-bit deep by 8-bit wide, multi-port, random access memory with synchronous writeand asynchronous independent, 2-bit, wide-read capability. This RAM is implemented using the LUT resourcesof the device known as SelectRAM, and does not consume any of the Block RAM resources of the device. TheRAM32M is implemented in a single slice and consists of one 8-bit write, 2-bit read port and three separate 2-bitread ports from the same memory. This configuration allows for byte-wide write and independent 2-bit readaccess RAM. If the DIA, DIB, DIC and DID inputs are all tied to the same data inputs, the RAM can becomea 1 read/write port, 3 independent read port, 32x2 quad port memory. If DID is grounded, DOD is not used,while ADDRA, ADDRB and ADDRC are tied to the same address, the RAM becomes a 32x6 simple dual portRAM. If ADDRD is tied to ADDRA, ADDRB, and ADDRC, then the RAM is a 32x8 single port RAM. There areseveral other possible configurations for this RAM.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 265

Chapter 4: About Design ElementsPort DescriptionsPort Direction Width FunctionDOA Output 2 Read port data outputs addressed by ADDRADOB Output 2 Read port data outputs addressed by ADDRBDOC Output 2 Read port data outputs addressed by ADDRCDOD Output 2 Read/Write port data outputs addressed by ADDRDDIA Input 2 Write data inputs addressed by ADDRD (read output isaddressed by ADDRA)DIB Input 2 Write data inputs addressed by ADDRD (read output isaddressed by ADDRB)DIC Input 2 Write data inputs addressed by ADDRD (read output isaddressed by ADDRC)DID Input 2 Write data inputs addressed by ADDRDADDRA Input 5 Read address bus AADDRB Input 5 Read address bus BADDRC Input 5 Read address bus CADDRD Input 5 8-bit data write port, 2-bit data read port address bus DWE Input 1 Write EnableWCLK Input 1 Write clock (reads are asynchronous)Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoThis element can be inferred by some synthesis tools by describing a RAM with a synchronous write andasynchronous read capability. Consult your synthesis tool documentation for details on RAM inferencecapabilities and coding examples. Xilinx suggests that you instantiate RAM32Ms if you have a need to implicitlyspecify the RAM function, or if you need to manually place or relationally place the component. If a synchronousread capability is desired, the RAM32M outputs can be connected to an FDRSE (FDCPE is asynchronous set/resetis necessary) in order to improve the output timing of the function. However, this is not necessary for theproper operation of the RAM.If you want to have the data clocked on the negative edge of a clock, an inverter can be described on the clockinput to this component. This inverter will be absorbed into the block, giving you the ability to write to the RAMon falling clock edges.If instantiated, the following connections should be made to this component. Tie the WCLK input to the desiredclock source, the DIA, DIB, DIC and DID inputs to the data source to be stored and the DOA, DOB, DOC andDOD outputs to an FDCE D input or other appropriate data destination or left unconnected if not used. The WEclock enable pin should be connected to the proper write enable source in the design. The 5-bit ADDRD busshould be connected to the source for the read/write addressing and the 5-bit ADDRA, ADDRB and ADDRCbuses should be connected to the appropriate read address connections. The optional INIT_A, INIT_B, INIT_Cand INIT_D attributes consisting of a 64-bit hexadecimal values that specifies each port’s initial memory contentscan be specified. The INIT value correlates to the RAM addressing by the following equation: ADDRy[z] =INIT_y[2*z+1:2*z]. For instance, if the RAM ADDRC port is addressed to 00001, then the INIT_C[3:2] valueswould be the initial values shown on the DOC port before the first write occurs at that address. If left unspecified,the initial contents will default to all zeros.Virtex-6 Libraries Guide for HDL Designs266 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT_A Hexadecimal Any 64-Bit Value All zeros Specifies the initial contents of the RAM onthe A port.INIT_B Hexadecimal Any 64-Bit Value All zeros Specifies the initial contents of the RAM onthe B port.INIT_C Hexadecimal Any 64-Bit Value All zeros Specifies the initial contents of the RAM onthe C port.INIT_D Hexadecimal Any 64-Bit Value All zeros Specifies the initial contents of the RAM onthe D port.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- RAM32M: 32-deep by 8-wide Multi Port LUT RAM-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2RAM32M_inst : RAM32Mgeneric map (INIT_A => X"0000000000000000",INIT_B => X"0000000000000000",INIT_C => X"0000000000000000",INIT_D => X"0000000000000000)port map (DOA => DOA, -- Read port A 2-bit outputDOB => DOB, -- Read port B 2-bit outputDOC => DOC, -- Read port C 2-bit outputDOD => DOD, -- Read/Write port D 2-bit output-- Initial contents of A port-- Initial contents of B port-- Initial contents of C port-- Initial contents of D portADDRA => ADDRA, -- Read port A 5-bit address inputADDRB => ADDRB, -- Read port B 5-bit address inputADDRC => ADDRC, -- Read port C 5-bit address inputADDRD => ADDRD, -- Read/Write port D 5-bit address inputDIA => DIA, -- RAM 2-bit data write input addressed by ADDRD,-- read addressed by ADDRADIB => DIB, -- RAM 2-bit data write input addressed by ADDRD,-- read addressed by ADDRBDIC => DIC, -- RAM 2-bit data write input addressed by ADDRD,-- read addressed by ADDRCDID => DID, -- RAM 2-bit data write input addressed by ADDRD,-- read addressed by ADDRDWCLK => WCLK, -- Write clock inputWE => WE -- Write enable input);-- End of RAM32M_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 267

Chapter 4: About Design ElementsVerilog Instantiation Template// RAM32M: 32-deep by 8-wide Multi Port LUT RAM// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2RAM32M #(.INIT_A(64’h0000000000000000), // Initial contents of A Port.INIT_B(64’h0000000000000000), // Initial contents of B Port.INIT_C(64’h0000000000000000), // Initial contents of C Port.INIT_D(64’h0000000000000000) // Initial contents of D Port) RAM32M_inst (.DOA(DOA), // Read port A 2-bit output.DOB(DOB), // Read port B 2-bit output.DOC(DOC), // Read port C 2-bit output.DOD(DOD), // Read/Write port D 2-bit output.ADDRA(ADDRA), // Read port A 5-bit address input.ADDRB(ADDRB), // Read port B 5-bit address input.ADDRC(ADDRC), // Read port C 5-bit address input.ADDRD(ADDRD), // Read/Write port D 5-bit address input.DIA(DIA), // RAM 2-bit data write input addressed by ADDRD,// read addressed by ADDRA.DIB(DIB), // RAM 2-bit data write input addressed by ADDRD,// read addressed by ADDRB.DIC(DIC), // RAM 2-bit data write input addressed by ADDRD,// read addressed by ADDRC.DID(DID), // RAM 2-bit data write input addressed by ADDRD,// read addressed by ADDRD.WCLK(WCLK), // Write clock input.WE(WE) // Write enable input);// End of RAM32M_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs268 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsRAM32X1SPrimitive: 32-Deep by 1-Wide Static Synchronous RAMIntroductionThe design element is a 32-word by 1-bit static random access memory with synchronous write capability. Whenthe write enable is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is notaffected. When (WE) is High, any positive transition on (WCLK) loads the data on the data input (D) into theword selected by the 5-bit address (A4-A0). For predictable performance, address and data inputs must be stablebefore a Low-to-High (WCLK) transition. This RAM block assumes an active-High (WCLK). However, (WCLK)can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbed into the block.The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by thevalues on the address pins. You can initialize RAM32X1S during configuration using the INIT attribute.Logic TableInputsWE (Mode) WCLK D OOutputs0 (read) X X Data1 (read) 0 X Data1 (read) 1 X Data1 (write) ↓ D D1 (read) ↑ X DataDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionsINIT Hexadecimal Any 32-Bit Value All zeros Specifies initial contents of the RAM.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 269

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- RAM32X1S: 32 x 1 posedge write distributed => LUT RAM-- All FPGA-- Xilinx HDL Libraries Guide, version 11.2RAM32X1S_inst : RAM32X1Sgeneric map (INIT => X"00000000")port map (O => O, -- RAM outputA0 => A0, -- RAM address[0] inputA1 => A1, -- RAM address[1] inputA2 => A2, -- RAM address[2] inputA3 => A3, -- RAM address[3] inputA4 => A4, -- RAM address[4] inputD => D, -- RAM data inputWCLK => WCLK, -- Write clock inputWE => WE -- Write enable input);-- End of RAM32X1S_inst instantiationVerilog Instantiation Template// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM// All FPGA// Xilinx HDL Libraries Guide, version 11.2RAM32X1S #(.INIT(32’h00000000) // Initial contents of RAM) RAM32X1S_inst (.O(O), // RAM output.A0(A0), // RAM address[0] input.A1(A1), // RAM address[1] input.A2(A2), // RAM address[2] input.A3(A3), // RAM address[3] input.A4(A4), // RAM address[4] input.D(D), // RAM data input.WCLK(WCLK), // Write clock input.WE(WE) // Write enable input);// End of RAM32X1S_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs270 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsRAM64MPrimitive: 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)IntroductionThis design element is a 64-bit deep by 4-bit wide, multi-port, random access memory with synchronous writeand asynchronous independent bit wide read capability. This RAM is implemented using the LUT resources ofthe device (also known as SelectRAM) and does not consume any of the block RAM resources of the device.The RAM64M component is implemented in a single slice, and consists of one 4-bit write, 1-bit read port,and three separate 1-bit read ports from the same memory allowing for 4-bit write and independent bit readaccess RAM. If the DIA, DIB, DIC and DID inputs are all tied to the same data inputs, the RAM can becomea 1 read/write port, 3 independent read port 64x1 quad port memory. If DID is grounded, DOD is not used.While ADDRA, ADDRB and ADDRC are tied to the same address the RAM becomes a 64x3 simple dual portRAM. If ADDRD is tied to ADDRA, ADDRB, and ADDRC; then the RAM is a 64x4 single port RAM. There areseveral other possible configurations for this RAM.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 271

Chapter 4: About Design ElementsPort DescriptionsPort Direction Width FunctionDOA Output 1 Read port data outputs addressed by ADDRADOB Output 1 Read port data outputs addressed by ADDRBDOC Output 1 Read port data outputs addressed by ADDRCDOD Output 1 Read/Write port data outputs addressed byADDRDDIA Input 1 Write data inputs addressed by ADDRD (readoutput is addressed by ADDRA)DIB Input 1 Write data inputs addressed by ADDRD (readoutput is addressed by ADDRB)DIC Input 1 Write data inputs addressed by ADDRD (readoutput is addressed by ADDRC)DID Input 1 Write data inputs addressed by ADDRDADDRA Input 6 Read address bus AADDRB Input 6 Read address bus BADDRC Input 6 Read address bus CADDRD Input 6 4-bit data write port, 1-bit data read portaddress bus DWE Input 1 Write EnableWCLK Input 1 Write clock (reads are asynchronous)Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoThis element can be inferred by some synthesis tools by describing a RAM with a synchronous write andasynchronous read capability. Consult your synthesis tool documentation for details on RAM inferencecapabilities and coding examples. Xilinx suggests that you instantiate RAM64Ms if you have a need to implicitlyspecify the RAM function, or if you need to manually place or relationally place the component. If a synchronousread capability is desired, the RAM64M outputs can be connected to an FDRSE (FDCPE is asynchronous set/resetis necessary) in order to improve the output timing of the function. However, this is not necessary for theproper operation of the RAM. If you want to have the data clocked on the negative edge of a clock, an invertercan be described on the clock input to this component. This inverter will be absorbed into the block giving theability to write to the RAM on falling clock edges.If instantiated, the following connections should be made to this component. Tie the WCLK input to thedesired clock source, the DIA, DIB, DIC and DID inputs to the data source to be stored and the DOA, DOB,DOC and DOD outputs to an FDCE D input or other appropriate data destination or left unconnected if notused. The WE clock enable pin should be connected to the proper write enable source in the design. The 5-bitADDRD bus should be connected to the source for the read/write addressing and the 5-bit ADDRA, ADDRBand ADDRC buses should be connected to the appropriate read address connections. The optional INIT_A,INIT_B, INIT_C and INIT_D attributes consisting of a 64-bit hexadecimal values that specifies each port’s initialmemory contents can be specified. The INIT value correlates to the RAM addressing by the following equation:ADDRy[z] = INIT_y[z].Virtex-6 Libraries Guide for HDL Designs272 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsFor instance, if the RAM ADDRC port is addressed to 00001, then the INIT_C[1] values would be the initialvalues shown on the DOC port before the first write occurs at that address. If left unspecified, the initial contentswill default to all zeros.Available AttributesAttribute Type Allowed Values Default DescriptionINIT_A Hexadecimal Any 64-Bit Value All zero Specifies the initial contents of the RAM onthe A port.INIT_B Hexadecimal Any 64-Bit Value All zero Specifies the initial contents of the RAM onthe B port.INIT_C Hexadecimal Any 64-Bit Value All zero Specifies the initial contents of the RAM onthe C port.INIT_D Hexadecimal Any 64-Bit Value All zero Specifies the initial contents of the RAM onthe D port.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- RAM64M: 64-deep by 4-wide Multi Port LUT RAM-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2RAM64M_inst : RAM64Mgeneric map (INIT_A => X"0000000000000000",INIT_B => X"0000000000000000",INIT_C => X"0000000000000000",INIT_D => X"0000000000000000)port map (DOA => DOA, -- Read port A 1-bit outputDOB => DOB, -- Read port B 1-bit outputDOC => DOC, -- Read port C 1-bit outputDOD => DOD, -- Read/Write port D 1-bit output-- Initial contents of A port-- Initial contents of B port-- Initial contents of C port-- Initial contents of D portADDRA => ADDRA, -- Read port A 6-bit address inputADDRB => ADDRB, -- Read port B 6-bit address inputADDRC => ADDRC, -- Read port C 6-bit address inputADDRD => ADDRD, -- Read/Write port D 6-bit address inputDIA => DIA, -- RAM 1-bit data write input addressed by ADDRD,-- read addressed by ADDRADIB => DIB, -- RAM 1-bit data write input addressed by ADDRD,-- read addressed by ADDRBDIC => DIC, -- RAM 1-bit data write input addressed by ADDRD,-- read addressed by ADDRCDID => DID, -- RAM 1-bit data write input addressed by ADDRD,-- read addressed by ADDRDWCLK => WCLK, -- Write clock inputWE => WE -- Write enable input);-- End of RAM64M_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 273

Chapter 4: About Design ElementsVerilog Instantiation Template// RAM64M: 64-deep by 4-wide Multi Port LUT RAM// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2RAM64M #(.INIT_A(64’h0000000000000000), // Initial contents of A Port.INIT_B(64’h0000000000000000), // Initial contents of B Port.INIT_C(64’h0000000000000000), // Initial contents of C Port.INIT_D(64’h0000000000000000) // Initial contents of D Port) RAM64M_inst (.DOA(DOA), // Read port A 1-bit output.DOB(DOB), // Read port B 1-bit output.DOC(DOC), // Read port C 1-bit output.DOD(DOD), // Read/Write port D 1-bit output.DIA(DIA), // RAM 1-bit data write input addressed by ADDRD,// read addressed by ADDRA.DIB(DIB), // RAM 1-bit data write input addressed by ADDRD,// read addressed by ADDRB.DIC(DIC), // RAM 1-bit data write input addressed by ADDRD,.DID(DID),// read addressed by ADDRC// RAM 1-bit data write input addressed by ADDRD,// read addressed by ADDRD.ADDRA(ADDRA), // Read port A 6-bit address input.ADDRB(ADDRB), // Read port B 6-bit address input.ADDRC(ADDRC), // Read port C 6-bit address input.ADDRD(ADDRD), // Read/Write port D 6-bit address input.WE(WE),.WCLK(WCLK));// Write enable input// Write clock input// End of RAM64M_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs274 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsRAM64X1DPrimitive: 64-Deep by 1-Wide Dual Port Static Synchronous RAMIntroductionThis design element is a 64-word by 1-bit static dual port random access memory with synchronous writecapability. The device has two separate address ports: the read address (DPRA5:DPRA0) and the write address(A5:A0). These two address ports are completely asynchronous. The read address controls the location ofthe data driven out of the output pin (DPO), and the write address controls the destination of a valid writetransaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and datastored in the RAM is not affected.When WE is High, any positive transition on WCLK loads the data on the data input (D) into the word selectedby the 6-bit (A0:A5) write address. For predictable performance, write address and data inputs must be stablebefore a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. WCLK can beactive-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.The SPO output reflects the data in the memory cell addressed by A5:A0. The DPO output reflects the datain the memory cell addressed by DPRA5:DPRA0.Note The write process is not affected by the address on the read address port.Logic TableInputsOutputsWE (mode) WCLK D SPO DPO0 (read) X X data_a data_d1 (read) 0 X data_a data_d1 (read) 1 X data_a data_d1 (write) ↑ D D data_d1 (read) ↓ X data_a data_ddata_a = word addressed by bits A5:A0data_d = word addressed by bits DPRA5:DPRA0Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 275

Chapter 4: About Design ElementsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 64-BitValueAll zerosInitializes RAMs, registers, and look-up tables.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- RAM64X1D: 64 x 1 positive edge write, asynchronous read dual-port distributed RAM-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2RAM64X1D_inst : RAM64X1Dgeneric map (INIT => X"0000000000000000")port map (DPO => DPO, -- Read-only 1-bit data outputSPO => SPO, -- R/W 1-bit data outputA0 => A0, -- R/W address[0] input bitA1 => A1, -- R/W address[1] input bitA2 => A2, -- R/W address[2] input bitA3 => A3, -- R/W address[3] input bitA4 => A4, -- R/W address[4] input bitA5 => A5, -- R/W address[5] input bitD => D,-- Write 1-bit data inputDPRA0 => DPRA0, -- address[0] input bitDPRA1 => DPRA1, -- Read-only address[1] input bitDPRA2 => DPRA2, -- Read-only address[2] input bitDPRA3 => DPRA3, -- Read-only address[3] input bitDPRA4 => DPRA4, -- Read-only address[4] input bitDPRA5 => DPRA5, -- Read-only address[5] input bitWCLK => WCLK, -- Write clock inputWE => WE -- Write enable input);-- End of RAM64X1D_inst instantiationVirtex-6 Libraries Guide for HDL Designs276 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// RAM64X1D: 64 x 1 positive edge write, asynchronous read dual-port distributed RAM// Virtex-5/6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2RAM64X1D #(.INIT(64’h0000000000000000) // Initial contents of RAM) RAM64X1D_inst (.DPO(DPO), // Read-only 1-bit data output.SPO(SPO), // R/W 1-bit data output.A0(A0), // R/W address[0] input bit.A1(A1), // R/W address[1] input bit.A2(A2), // R/W address[2] input bit.A3(A3), // R/W address[3] input bit.A4(A4), // R/W address[4] input bit.A5(A5), // R/W address[5] input bit.D(D),// Write 1-bit data input.DPRA0(DPRA0), // Read-only address[0] input bit.DPRA1(DPRA1), // Read-only address[1] input bit.DPRA2(DPRA2), // Read-only address[2] input bit.DPRA3(DPRA3), // Read-only address[3] input bit.DPRA4(DPRA4), // Read-only address[4] input bit.DPRA5(DPRA5), // Read-only address[5] input bit.WCLK(WCLK), // Write clock input.WE(WE) // Write enable input);// End of RAM64X1D_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 277

Chapter 4: About Design ElementsRAM64X1SPrimitive: 64-Deep by 1-Wide Static Synchronous RAMIntroductionThis design element is a 64-word by 1-bit static random access memory (RAM) with synchronous write capability.When the write enable is set Low, transitions on the write clock (WCLK) are ignored and data stored in the RAMis not affected. When WE is set High, any positive transition on WCLK loads the data on the data input (D)into the word selected by the 6-bit address (A5:A0). This RAM block assumes an active-High WCLK. However,WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined bythe values on the address pins.You can initialize this element during configuration using the INIT attribute.Logic TableMode selection is shown in the following logic tableInputsWE (mode) WCLK D O0 (read) X X Data1 (read) 0 X Data1 (read) 1 X Data1 (write) ↑ D D1 (read) ↓ X DataData = word addressed by bits A5:A0OutputsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 64-Bit Value All zeros Initializes ROMs, RAMs, registers, and look-uptables.Virtex-6 Libraries Guide for HDL Designs278 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM-- Virtex-4/5, Spartan-3/3E/3A-- Xilinx HDL Libraries Guide, version 11.2RAM64X1S_inst : RAM64X1Sgeneric map (INIT => X"0000000000000000")port map (O => O, -- 1-bit data outputA0 => A0, -- Address[0] input bitA1 => A1, -- Address[1] input bitA2 => A2, -- Address[2] input bitA3 => A3, -- Address[3] input bitA4 => A4, -- Address[4] input bitA5 => A5, -- Address[5] input bitD => D, -- 1-bit data inputWCLK => WCLK, -- Write clock inputWE => WE -- Write enable input);-- End of RAM64X1S_inst instantiationVerilog Instantiation Template// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM// All FPGA// Xilinx HDL Libraries Guide, version 11.2RAM64X1S #(.INIT(64’h0000000000000000) // Initial contents of RAM) RAM64X1S_inst (.O(O), // 1-bit data output.A0(A0), // Address[0] input bit.A1(A1), // Address[1] input bit.A2(A2), // Address[2] input bit.A3(A3), // Address[3] input bit.A4(A4), // Address[4] input bit.A5(A5), // Address[5] input bit.D(D), // 1-bit data input.WCLK(WCLK), // Write clock input.WE(WE) // Write enable input);// End of RAM64X1S_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 279

Chapter 4: About Design ElementsRAMB18E1Primitive: 18K-bit Configurable Synchronous Block RAMIntroductionVirtex®-6 devices contain several block RAM memories that can be configured as FIFOs, automatic errorcorrection RAM, or general-purpose 36 kb or 18 kb RAM/ROM memories. These block RAM memories offer fastand flexible storage of large amounts of on-chip data. This element allows access to the block RAM in the 18 kbconfiguration. This element can be configured and used as a 1-bit wide by 16K deep to an 18-bit wide by 1029-bitdeep true dual port RAM. This element can also be configured as a 36-bit wide by 512 deep simple dual portRAM. Both read and write operations are fully synchronous to the supplied clock(s) in the component. However,the READ and WRITE ports can operate fully independently and asynchronously to each other, accessing thesame memory array. When configured in the wider data width modes, byte-enable write operations are possible,and an optional output register can be used to reduce the clock-to-out times of the RAM.Port DescriptionsPort Type Width FunctionADDRARDADDR[13:0] Input 14 Port A address input bus/Read address input bus.ADDRBWRADDR[13:0] Input 14 Port B address input bus/Write address input bus.CLKARDCLK Input 1 Port A clock input/Read clock input.Virtex-6 Libraries Guide for HDL Designs280 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPort Type Width FunctionCLkbWRCLK Input 1 Port B clock input/Write clock input.DIADI[15:0] Input 16 Port A data input bus/Data input bus addressed by WRADDR.When RAM_MODE=SDP, DIADI is the logical DI[15:0].DIBDI[15:0] Input 16 Port B data input bus/Data input bus addressed by WRADDR.When RAM_MODE=SDP, DIBDI is the logical DI[31:16].DIPADIP[1:0] Input 2 Port A parity data input bus/Data parity input bus addressedby WRADDR. When RAM_MODE=SDP, DIPADIP is the logicalDIP[1:0].DIPBDIP[1:0] Input 2 Port B parity data input bus/Data parity input bus addressedby WRADDR. When RAM_MODE=SDP, DIPBDIP is the logicalDIP[3:2].DOADO[15:0] Output 16 Port A data output bus/Data output bus addressed by RDADDR.When RAM_MODE=SDP, DOADO is the logical DO[15:0].DOBDO[15:0] Output 16 Port B data output bus/Data output bus addressed by RDADDR.When RAM_MODE=SDP, DOBDO is the logical DO[31:16].DOPADOP[1:0] Output 2 Port A parity data output bus/Data parity output bus addressedby RDADDR. When RAM_MODE=SDP, DOPADOP is the logicalDOP[1:0].DOPBDOP[1:0] Output 2 Port B parity data output bus/Data parity output bus addressedby RDADDR. When RAM_MODE=SDP, DOPBDOP is the logicalDOP[3:2].ENARDEN Input 1 Port A RAM enable/Read enable.ENBWREN Input 1 Port B RAM enable/Write enable.REGCEAREGCE Input 1 Port A output register clock enable input/Output register clockenable input (valid only when DO_REG=1).REGCEB Input 1 Port B output register clock enable (valid only when DO_REG=1and RAM_MODE=TDP).RSTRAMARSTRAM Input 1 Synchronous data latch set/reset to value indicated by SRVAL_A.RSTRAMARSTRAM sets/resets the BRAM data output latch whenDO_REG=0 or 1. If DO_REG=1 there is a cycle of latency betweenthe internal data latch node that is reset by RSTRAMARSTRAMand the DO output of the BRAM. This signal is RSTRAMAon port A when RAM_MODE=TDP and RSTRAM whenRAM_MODE=SDP.RSTRAMB Input 1 Synchronous data latch set/reset to value indicated by SRVAL_B.RSTRAMB sets/resets the BRAM data output latch whenDO_REG=0 or 1. If DO_REG=1 there is a cycle of latency betweenthe internal data latch node that is reset by RSTRAMB and the DOoutput of the BRAM. Not used when RAM_MODE=SDP.RSTREGARSTREG Input 1 Synchronous output register set/reset to value indicated bySRVAL_A. RSTREGARSTREG sets/resets the output register whenDO_REG=1. RSTREG_PRIORITY_A determines if this signal getspriority over REGCEAREGCE. This signal is RSTREGA on port Awhen RAM_MODE=TDP and RSTREG when RAM_MODE=SDP.RSTREGB Input 1 Synchronous output register set/reset to value indicated bySRVAL_B. RSTREGB sets/resets the output register whenDO_REG=1. RSTREG_PRIORITY_B determines if this signal getspriority over REGCEB. Not used when RAM_MODE=SDP.WEA[1:0] Input 2 Port A byte-wide write enable. Not used when RAM_MODE=SDP.See User Guide for WEA mapping for different port widths.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 281

Chapter 4: About Design ElementsPort Type Width FunctionWEBWE[3:0] Input 4 Port B byte-wide write enable/Write enable. See User Guide forWEBWE mapping for different port widths.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionDOA_REG Integer 0, 1 0 A value of 1 enables the outputregisters to the RAM enabling quickerclock-to-out from the RAM at theexpense of an added clock cycle of readlatency. A value of 0 allows a read inone clock cycle but will result in slowerclock-to-out timing. Applies to port Ain TDP mode and up to 18 lower bits(including parity bits) in SDP mode.DOB_REG Integer 0, 1 0 A value of 1 enables the outputregisters to the RAM enabling quickerclock-to-out from the RAM at theexpense of an added clock cycle ofread latency. A value of 0 allows aread in one clock cycle but will resultin slower clock-to-out timing. Appliesto port B in TDP mode and upper bits(including parity bits) in SDP mode.INIT_AINIT_BAny 18 Bit Value All zeros Specifies the initial value on the PortA output after configuration. Appliesto port A in TDP mode and up to 18lower bits (including parity bits) inSDP mode.Any 18 Bit Value All zeros Specifies the initial value on the PortB output after configuration. Appliesto port B in TDP mode and upper bits(including parity bits) in SDP mode.INIT_FILE String 0 bit String None File name of file used to specify initialRAM contents.INITIALDATAHexadecimalHexadecimalHexadecimal256’h0000000000000000000000000000000000000000000000000000000000000000 to256’h000000000000000000000000000000000000000000001.15792089237316e+77All zerosAllows specification of the initialcontents of the 16 kb data memoryarray.Virtex-6 Libraries Guide for HDL Designs282 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionINITIALPARITYHexadecimal256’h0000000000000000000000000000000000000000000000000000000000000000 to256’h000000000000000000000000000000000000000000001.15792089237316e+77All zerosAllows specification of the initialcontents of the 2 kb parity datamemory array.RAM_MODE String “TDP”,” SDP” “TDP” Selects simple dual port (SDP) or truedual port (TDP) mode.READ_WIDTH_A Integer 0, 1, 2, 4, 9, 18, 36, 72 0 Specifies the desired data width for aread on Port A, including parity bits.This value must be 0 if the Port A is notused. Otherwise, it should be set to thedesired port width. In SDP mode, thisis the read width including parity bits.READ_WIDTH_B Integer 0, 1, 2, 4, 9, 18 0 Specifies the desired data width for aread on Port B including parity bits.This value must be 0 if the Port B is notused. Otherwise, it should be set tothe desired port width. Not used forSDP mode.RSTREG_PRIORITY_A String “RSTREG”,“REGCE”RSTREG_PRIORITY_B String “RSTREG”,“REGCE”SIM_COLLISION_CHECKString“ALL”,”WARNING_ONLY”,”GENERATE_X_ONLY”,”NONE”“RSTREG”“RSTREG”“ALL”Selects register priority for RSTREGor REGCE. Applies to port A inTDP mode and up to 18 lower bits(including parity bits) in SDP mode.Selects register priority for RSTREGor REGCE. Applies to port B in TDPmode and upper bits (including paritybits) in SDP mode.Allows modification of the simulationbehavior if a memory collision occurs:• ALL - warning produced andaffected outputs/memory locationgo unknown (X).• WARNING_ONLY -warningproduced and affectedoutputs/memory retain lastvalue.• GENERATE_X_ONLY - nowarning however affectedoutputs/memory go unknown (X).• NONE - no warning and affectedoutputs/memory retain last value.Note ALL can allow problems inthe design go unnoticed duringsimulation. Care should be takenwhen changing the value of thisattribute.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 283

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionSRVAL_ASRVAL_BHexadecimalHexadecimalWRITEMODE String “WRITE_FIRST”,“READ_FIRST”“NO_CHANGE”Any 18 Bit Value All zeros Specifies the output value of the RAMupon assertion of the synchronousreset (RSTREG) signal. Applies to portA in TDP mode and up to 18 lower bits(including parity bits) in SDP mode.Any 18 Bit Value All zeros Specifies the output value of the RAMupon assertion of the synchronousreset (RSTREG) signal. Applies toport B in TDP mode and upper bits(including parity bits) in SDP mode.“WRITE_FIRST”Specifies output behavior of the portbeing written to:• WRITE_FIRST - written valueappears on output port of theRAM• READ_FIRST – previous RAMcontents for that memory locationappear on the output port• NO_CHANGE – previous valueon the output port remains thesame.Default is WRITE_FIRST in TDPmode. Must equal READ_FIRST inSDP mode.WRITE_WIDTH_A Integer 0, 1, 2, 4, 9, 18 0 Specifies the desired data width for awrite to Port A including parity bits.This value must be 0 if the port is notused. Otherwise should be set to thedesired write width. Not used in SDPmode.WRITE_WIDTH_B Integer 0, 1, 2, 4, 9, 18, 36, 72 0 Specifies the desired data width for awrite to Port B including parity bits.This value must be 0 if the port is notused. Otherwise should be set to thedesired write width. In SDP mode, thisis the write width including parity bits.VHDL Instantiation Template-- RAMB18E1: 18K-bit Configurable Synchronous Block RAM-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2RAMB18E1_inst : RAMB18E1generic map (DOA_REG => 0,DOB_REG => 0,-- Optional output-- register on A port (0-- or 1)-- Optional output-- register on B port (0-- or 1)-- INITP_00 to INITP_07: Allows specification of the initial contents of the 2KB parity data memory-- array.INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",Virtex-6 Libraries Guide for HDL Designs284 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsINITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",-- INIT_00 to INIT_3F: Allows specification of the initial contents of the 16KB data memory array.INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_A => X"0000000",-- Initial values on A-- output portINIT_B => X"0000000",-- Initial values on B-- output portINIT_FILE => "NONE",-- File name of file-- used to specify-- initial RAM contents.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 285

Chapter 4: About Design ElementsRAM_MODE => "TDP",-- SDP or TDPREAD_WIDTH_A => 0,-- 0, 1, 2, 4, 9, 18, or-- 36READ_WIDTH_B => 0, -- 0, 1, 2, 4, 9, 18RSTREG_PRIORITY_A => "RSTREG",-- RSTREG or REGCERSTREG_PRIORITY_B => "RSTREG",-- RSTREG or REGCESIM_COLLISION_CHECK => "ALL",-- Collision check-- enable "ALL",-- "WARNING_ONLY",-- "GENERATE_X_ONLY" or-- "NONE"SRVAL_A => X"0000000",-- Set/Reset value for A-- port outputSRVAL_B => X"0000000",-- Set/Reset value for B-- port outputWRITE_WIDTH_A => 0, -- 0, 1, 2, 4, 9, or 18WRITE_WIDTH_B => 0,-- 0, 1, 2, 4, 9, 18, or-- 36-- WriteMode: Specifies output behavior of the port being written to: "WRITE_FIRST" = written value-- appears on output port of the RAM "READ_FIRST" = previous RAM contents for that memory location appear-- on the output port "NO_CHANGE" = previous value on the output port remains the same. Default is-- WRITE_FIRST in TDP mode. Must equal READ_FIRST in SDP mode.WRITE_MODE_A => "WRITE_FIRST",WRITE_MODE_B => "WRITE_FIRST")port map (DOADO => DOADO,-- 16-bit A port data/LSB data outputDOBDO => DOBDO,-- 16-bit B port data/MSB data outputDOPADOP => DOPADOP,-- 2-bit A port parity/LSB parity outputDOPBDOP => DOPBDOP,-- 2-bit B port parity/MSB parity outputADDRARDADDR => ADDRARDADDR, -- 14-bit A port address/Read address inputADDRBWRADDR => ADDRBWRADDR, -- 14-bit B port address/Write address inputCLKARDCLK => CLKARDCLK,-- 1-bit A port clock/Read clock inputCLKBWRCLK => CLKBWRCLK,-- 1-bit B port clock/Write clock inputDIADI => DIADI,-- 16-bit A port data/LSB data inputDIBDI => DIBDI,-- 16-bit B port data/MSB data inputDIPADIP => DIPADIP,-- 2-bit A port parity/LSB parity inputDIPBDIP => DIPBDIP,-- 2-bit B port parity/MSB parity inputENARDEN => ENARDEN,-- 1-bit A port enable/Read enable inputENBWREN => ENBWREN,-- 1-bit B port enable/Write enable inputREGCEAREGCE => REGCEAREGCE, -- 1-bit A port register enable/Register enable inputREGCEB => REGCEB,-- 1-bit B port register enable inputRSTRAMARSTRAM => RSTRAMARSTRAM, -- 1-bit A port set/reset inputRSTRAMB => RSTRAMB,-- 1-bit B port set/reset inputRSTREGARSTREG => RSTREGARSTREG, -- 1-bit A port register set/reset inputRSTREGB => RSTREGB,-- 1-bit B port register set/reset inputWEA => WEA,-- 2-bit A port write enable inputWEBWE => WEBWE-- 4-bit B port write enable/Write enable input);-- End of RAMB18E1_inst instantiation-- "WRITE_FIRST",-- "READ_FIRST", or-- "NO_CHANGE"-- "WRITE_FIRST",-- "READ_FIRST", or-- "NO_CHANGE"Verilog Instantiation Template// RAMB18E1: 18K-bit Configurable Synchronous Block RAM// Virtex-6// Xilinx HDL Language Template, version 11.1RAMB18E1 #(.DOA_REG(0),.DOB_REG(0),// Optional output// register on A port// (0 or 1)// Optional output// register on B port// (0 or 1)// INITP_00 to INITP_07: Allows specification of the initial contents of the 2KB parity data memory// array..INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),Virtex-6 Libraries Guide for HDL Designs286 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design Elements.INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000),// INIT_00 to INIT_3F: Allows specification of the initial contents of the 16KB data memory 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Initial values on AVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 287

Chapter 4: About Design Elements// output port.INIT_B(18’h00000),// Initial values on B// output port.INIT_FILE("NONE"),// File name of file// used to specify// initial RAM// contents..RAM_MODE("TDP"),// SDP or TDP.READ_WIDTH_A(0), // 0, 1, 2, 4, 9, 18,// or 36.READ_WIDTH_B(0), // 0, 1, 2, 4, 9, 18.RSTREG_PRIORITY_A("RSTREG"),// RSTREG or REGCE.RSTREG_PRIORITY_B("RSTREG"),// RSTREG or REGCE.SIM_COLLISION_CHECK("ALL"),// Collision check// enable "ALL",// "WARNING_ONLY",// "GENERATE_X_ONLY" or// "NONE".SRVAL_A(18’h00000),// Set/Reset value for// A port output.SRVAL_B(18’h00000),// Set/Reset value for// B port output.WRITE_WIDTH_A(0), // 0, 1, 2, 4, 9, or 18.WRITE_WIDTH_B(0), // 0, 1, 2, 4, 9, 18,// or 36// WriteMode: Specifies output behavior of the port being written to: "WRITE_FIRST" = written value// appears on output port of the RAM "READ_FIRST" = previous RAM contents for that memory location appear// on the output port "NO_CHANGE" = previous value on the output port remains the same. Default is// WRITE_FIRST in TDP mode. Must equal READ_FIRST in SDP mode..WRITE_MODE_A("WRITE_FIRST"),.WRITE_MODE_B("WRITE_FIRST"))RAMB18E1_inst (.DOADO(DOADO),// 16-bit A port data/LSB data output.DOBDO(DOBDO),// 16-bit B port data/MSB data output.DOPADOP(DOPADOP),// 2-bit A port parity/LSB parity output.DOPBDOP(DOPBDOP),// 2-bit B port parity/MSB parity output.ADDRARDADDR(ADDRARDADDR), // 14-bit A port address/Read address input.ADDRBWRADDR(ADDRBWRADDR), // 14-bit B port address/Write address input.CLKARDCLK(CLKARDCLK),// 1-bit A port clock/Read clock input.CLKBWRCLK(CLKBWRCLK),// 1-bit B port clock/Write clock input.DIADI(DIADI),// 16-bit A port data/LSB data input.DIBDI(DIBDI),// 16-bit B port data/MSB data input.DIPADIP(DIPADIP),// 2-bit A port parity/LSB parity input.DIPBDIP(DIPBDIP),// 2-bit B port parity/MSB parity input.ENARDEN(ENARDEN),// 1-bit A port enable/Read enable input.ENBWREN(ENBWREN),// 1-bit B port enable/Write enable input.REGCEAREGCE(REGCEAREGCE), // 1-bit A port register enable/Register enable input.REGCEB(REGCEB),// 1-bit B port register enable input.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit A port set/reset input.RSTRAMB(RSTRAMB),// 1-bit B port set/reset input.RSTREGARSTREG(RSTREGARSTREG), // 1-bit A port register set/reset input.RSTREGB(RSTREGB),// 1-bit B port register set/reset input.WEA(WEA),// 2-bit A port write enable input.WEBWE(WEBWE)// 4-bit B port write enable/Write enable input);// End of RAMB18E1_inst instantiation// "WRITE_FIRST",// "READ_FIRST", or// "NO_CHANGE"// "WRITE_FIRST",// "READ_FIRST", or// "NO_CHANGE"For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs288 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsRAMB36E1Primitive: 36K-bit Configurable Synchronous Block RAMIntroductionVirtex®-6 devices contain several block RAM memories that can be configured as FIFOs, automaticerror-correction RAM, or general-purpose 36 kb or 18 kb RAM/ROM memories. These Block RAM memoriesoffer fast and flexible storage of large amounts of on-chip data. This element allows access to the Block RAMin the 36 kb configurations. This element can be cascaded to create a larger RAM. This component can beconfigured and used as a 1-bit wide by 32K deep to a 36-bit wide by 1K deep true dual port RAM. Both readand write operations are fully synchronous to the supplied clock(s) in the component. However, the READ andWRITE ports can operate fully independently and asynchronously of each other, accessing the same memoryarray. When configured in the wider data width modes, byte-enable write operations are possible, and anoptional output register can be used to reduce the clock-to-out times of the RAM. Error detection and correctioncircuitry can also be enabled to uncover and rectify possible memory corruption.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 289

Chapter 4: About Design ElementsPort DescriptionsPort Type Width FunctionADDRARDADDR[15:0] Input 16 Port A address input bus/Read address input bus.ADDRBWRADDR[15:0] Input 16 Port B address input bus/Write address input bus.CASCADEINA Input 1 Port A cascade input. Never use when RAM_MODE=SDP.CASCADEINB Input 1 Port B cascade input. Never use when RAM_MODE=SDP.CASCADEOUTA Output 1 Port A cascade output. Never use when RAM_MODE=SDP.CASCADEOUTB Output 1 Port B cascade output. Never use when RAM_MODE=SDP.CLKARDCLK Input 1 Port A clock input/Read clock input.CLKBWRCLK Input 1 Port B clock input/Write clock input.DBITERR Output 1 Status output from ECC function to indicate a double bit error wasdetected. Set EN_ECC_READ to TRUE to use this functionality.Not used when RAM_MODE=TDP.DIADI[31:0] Input 32 Port A data input bus/Data input bus addressed by WRADDR.When RAM_MODE=SDP, DIADI is the logical DI[31:0].DIBDI[31:0] Input 32 Port B data input bus/Data input bus addressed by WRADDR.When RAM_MODE=SDP, DIBDI is the logical DI[63:32].DIPADIP[3:0] Input 4 Port A parity data input bus/Data parity input bus addressedby WRADDR. When RAM_MODE=SDP, DIPADIP is the logicalDIP[3:0].DIPBDIP[3:0] Input 4 Port B parity data input bus/Data parity input bus addressedby WRADDR. When RAM_MODE=SDP, DIPBDIP is the logicalDIP[7:4].DOADO[31:0] Output 32 Port A data output bus/Data output bus addressed by RDADDR.When RAM_MODE=SDP, DOADO is the logical DO[31:0].DOBDO[31:0] Output 32 Port B data output bus/Data output bus addressed by RDADDR.When RAM_MODE=SDP, DOBDO is the logical DO[63:32].DOPADOP[3:0] Output 4 Port A parity data output bus/Data parity output bus addressedby RDADDR. When RAM_MODE=SDP, DOPADOP is the logicalDOP[3:0].DOPBDOP[3:0] Output 4 Port B parity data output bus/Data parity output bus addressedby RDADDR. When RAM_MODE=SDP, DOPBDOP is the logicalDOP[7:4].ECCPARITY[7:0] Output 8 8-bit data generated by the ECC encoder used by the ECCdecoder for memory error detection and correction. Not used ifRAM_MODE=TDP.ENARDEN Input 1 Port A RAM enable/Read enable.ENBWREN Input 1 Port B RAM enable/Write enable.INJECTDBITERR Input 1 Inject a double bit error if ECC feature is used.INJECTSBITERR Input 1 Inject a single bit error if ECC feature is used.RDADDRECC[8:0] Output 9 9-bit ECC read address. Not used when RAM_MODE=TDP.REGCEAREGCE Input 1 Port A output register clock enable input/Output register clockenable input (valid only when DO_REG=1).REGCEB Input 1 Port B output register clock enable (valid only when DO_REG=1and RAM_MODE=TDP).Virtex-6 Libraries Guide for HDL Designs290 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPort Type Width FunctionRSTRAMARSTRAM Input 1 Synchronous data latch set/reset to value indicated by SRVAL_A.RSTRAMARSTRAM sets/resets the BRAM data output latch whenDO_REG=0 or 1. If DO_REG=1 there is a cycle of latency betweenthe internal data latch node that is reset by RSTRAMARSTRAMand the DO output of the BRAM. This signal is RSTRAMAon port A when RAM_MODE=TDP and RSTRAM whenRAM_MODE=SDP.RSTRAMB Input 1 Synchronous data latch set/reset to value indicated by SRVAL_B.RSTRAMB sets/resets the BRAM data output latch whenDO_REG=0 or 1. If DO_REG=1 there is a cycle of latency betweenthe internal data latch node that is reset by RSTRAMB and the DOoutput of the BRAM. Not used when RAM_MODE=SDP.RSTREGARSTREG Input 1 Synchronous output register set/reset to value indicated bySRVAL_A. RSTREGARSTREG sets/resets the output register whenDO_REG=1. RSTREG_PRIORITY_A determines if this signal getspriority over REGCEAREGCE. This signal is RSTREGA on port Awhen RAM_MODE=TDP and RSTREG when RAM_MODE=SDP.RSTREGB Input 1 Synchronous output register set/reset to value indicated bySRVAL_B. RSTREGB sets/resets the output register whenDO_REG=1. RSTREG_PRIORITY_B determines if this signal getspriority over REGCEB. Not used when RAM_MODE=SDP.SBITERR Output 1 Status output from ECC function to indicate a single bit error wasdetected. EN_ECC_READ needs to be TRUE in order to use thisfunctionality. Not used when RAM_MODE=TDP.WEA[3:0] Input 4 Port A byte-wide write enable. Not used when RAM_MODE=SDP.See User Guide for WEA mapping for different port widths.WEBWE[7:0] Input 8 Port B byte-wide write enable/Write enable. See Virtex®-6 UserGuide for WEBWE mapping for different port widths.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedAvailable AttributesAttribute Type Allowed Values Default DescriptionDOA_REG Integer 0, 1 0 A value of 1 enables the output registersto the RAM enabling quicker clock-to-outfrom the RAM at the expense of anadded clock cycle of read latency. Avalue of 0 allows a read in one clock cyclebut will result in slower clock-to-outtiming. Applies to port A in TDP modeand up to 36 lower bits (including paritybits) in SDP mode.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 291

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionDOB_REG Integer 0, 1 0 A value of 1 enables the output registersto the RAM enabling quicker clock-to-outfrom the RAM at the expense of anadded clock cycle of read latency. Avalue of 0 allows a read in one clock cyclebut will result in slower clock-to-outtiming. Applies to port B in TDP modeand upper bits (including parity bits) inSDP mode.EN_ECC_READ Boolean FALSE, TRUE FALSE Enable the ECC decoder circuitry.EN_ECC_WRITE Boolean FALSE, TRUE FALSE Enable the ECC encoder circuitry.INIT_AINIT_BAny 36 bit Value All zeros Specifies the initial value on the Port Aoutput after configuration. Applies toport A in TDP mode and up to 36 lowerbits (including parity bits) in SDP mode.Any 36 bit Value All zeros Specifies the initial value on the PortB output after configuration. Appliesto port B in TDP mode and upper bits(including parity bits) in SDP mode.INIT_FILE String 0 bit String NONE File name of file used to specify initialRAM contents.INIT_00 toINIT_7FINITP_00 toINITP_0FHexadecimalHexadecimalHexadecimalHexadecimal256’h0000000000000000000000000000000000000000000000000000000000000000 to256’h000000000000000000000000000000000000000000001.15792089237316e+77256’h0000000000000000000000000000000000000000000000000000000000000000 to256’h000000000000000000000000000000000000000000001.15792089237316e+77RAM_EXTENSION_A String “NONE”,“LOWER”,“UPPER”All zerosAll zeros“NONE”Allows specification of the initialcontents of the 32 kb data memory array.Allows specification of the initialcontents of the 4 kb parity data memoryarray.Selects port A cascade mode. If notcascading two block RAMs to forma 72K x 1 RAM, set to "NONE". Ifcascading RAMs, set to either "UPPER"or "LOWER" to indicate relative RAMlocation for proper configuration of theRAM. Not used if RAM_MODE=SDP.Virtex-6 Libraries Guide for HDL Designs292 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionRAM_EXTENSION_B String “NONE”,“LOWER”,“UPPER”“NONE”Selects port B cascade mode. If notcascading two block RAMs to forma 72K x 1 RAM, set to "NONE". Ifcascading RAMs, set to either "UPPER"or "LOWER" to indicate relative RAMlocation for proper configuration of theRAM. Not used if RAM_MODE=SDP.RAM_MODE String “TDP”, “SDP” “TDP” Selects simple dual port (SDP) or truedual port (TDP) mode.READ_WIDTH_A Integer 0, 1, 2, 4, 9, 18, 36,720 Specifies the desired data width for aread on Port A, including parity bits.This value must be 0 if the Port A is notused. Otherwise, it should be set to thedesired port width. In SDP mode, this isthe read width including parity bits.READ_WIDTH_B Integer 0, 1, 2, 4, 9, 18, 36 0 Specifies the desired data width for aread on Port B including parity bits. Thisvalue must be 0 if the Port B is not used.Otherwise, it should be set to the desiredport width. Not used for SDP mode.RSTREG_PRIORITY_A String “RSTREG”,“REGCE”RSTREG_PRIORITY_B String “RSTREG”,“REGCE”SIM_COLLISION_CHECKSRVAL_AStringHexadecimal“ALL”,“GENERATE_X_ONLY”,“NONE”,“WARNING_ONLY”“RSTREG”“RSTREG”ALLSelects register priority for RSTREG orREGCE. Applies to port A in TDP modeand up to 36 lower bits (including paritybits) in SDP mode.Selects register priority for RSTREG orREGCE. Applies to port B in TDP modeand upper bits (including parity bits) inSDP mode.Allows modification of the simulationbehavior if a memory collision occurs:• ALL - warning produced andaffected outputs/memory locationgo unknown (X)• WARNING_ONLY - warningproduced and affectedoutputs/memory retain last value• GENERATE_X_ONLY - no warninghowever affected outputs/memorygo unknown (X)• NONE - no warning and affectedoutputs/memory retain last value.Note Setting this to a value other than"ALL" can allow problems in the designgo unnoticed during simulation. Careshould be taken when changing thevalue of this attribute.Any 36 bit Value All zeros Specifies the output value of the RAMupon assertion of the synchronous reset(RSTREG) signal. Applies to port Ain TDP mode and up to 36 lower bits(including parity bits) in SDP mode.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 293

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionSRVAL_BHexadecimalWRITEMODE String “WRITE_FIRST”,“READ_FIRST”,“NO_CHANGE”,Any 36 bit Value All zeros Specifies the output value of the RAMupon assertion of the synchronous reset(RSTREG) signal. Applies to port B inTDP mode and upper bits (includingparity bits) in SDP mode.“WRITE_FIRST”Specifies output behavior of the portbeing written to:• WRITE_FIRST - written valueappears on output port of the RAM• READ_FIRST - previous RAMcontents for that memory locationappear on the output port• NO_CHANGE - previous value onthe output port remains the same.Default is WRITE_FIRST in TDP mode.Must equal READ_FIRST in SDP mode.WRITE_WIDTH_A Integer 0, 1, 2, 4, 9, 18, 36 0 Specifies the desired data width for awrite to Port A including parity bits. Thisvalue must be 0 if the port is not used.Otherwise should be set to the desiredwrite width. Not used in SDP mode.WRITE_WIDTH_B Integer 0, 1, 2, 4, 9, 18, 36,720 Specifies the desired data width for awrite to Port B including parity bits. Thisvalue must be 0 if the port is not used.Otherwise should be set to the desiredwrite width. In SDP mode, this is thewrite width including parity bits.VHDL Instantiation Template-- RAMB36E1: 36K-bit Configurable Synchronous Block RAM-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2RAMB36E1_inst : RAMB36E1generic map (DOA_REG => 0,DOB_REG => 0,EN_ECC_READ => FALSE,EN_ECC_WRITE => FALSE,-- Optional output-- register on A port (0-- or 1)-- Optional output-- register on B port (0-- or 1)-- Enable ECC decoder,-- TRUE or FALSE-- Enable ECC encoder,-- TRUE or FALSE-- INITP_00 to INITP_0F: Allows specification of the initial contents of the 4KB parity data memory-- array.INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",Virtex-6 Libraries Guide for HDL Designs294 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsINITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",-- INIT_00 to INIT_7F: Allows specification of the initial contents of the 32KB data memory array.INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_08 => 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Chapter 4: About Design ElementsINIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_52 => 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Chapter 4: About Design ElementsRSTREG_PRIORITY_A => "RSTREG",RSTREG_PRIORITY_B => "RSTREG",SIM_COLLISION_CHECK => "ALL",SRVAL_A => X"000000000",SRVAL_B => X"000000000",WRITE_WIDTH_A => 0,-- 36-- RSTREG or REGCE-- RSTREG or REGCE-- Collision check-- enable "ALL",-- "WARNING_ONLY",-- "GENERATE_X_ONLY" or-- "NONE"-- Set/Reset value for A-- port output-- Set/Reset value for B-- port output-- 0, 1, 2, 4, 9, 18, or-- 36WRITE_WIDTH_B => 0, -- 0, 1, 2, 4, 9, 18,-- 36, or 72-- WriteMode: Specifies output behavior of the port being written to: "WRITE_FIRST" = written value-- appears on output port of the RAM "READ_FIRST" = previous RAM contents for that memory location appear-- on the output port "NO_CHANGE" = previous value on the output port remains the same. Default is-- WRITE_FIRST in TDP mode. Must equal READ_FIRST in SDP mode.WRITE_MODE_A => "WRITE_FIRST",WRITE_MODE_B => "WRITE_FIRST")port map (CASCADEOUTA => CASCADEOUTA, -- 1-bit A port cascade outputCASCADEOUTB => CASCADEOUTB, -- 1-bit B port cascade outputDBITERR => DBITERR,-- 1-bit double bit error status outputDOADO => DOADO,-- 32-bit A port data/LSB data outputDOBDO => DOBDO,-- 32-bit B port data/MSB data outputDOPADOP => DOPADOP,-- 4-bit A port parity/LSB parity outputDOPBDOP => DOPBDOP,-- 4-bit B port parity/MSB parity outputECCPARITY => ECCPARITY,-- 8-bit generated error correction parityRDADDRECC => RDADDRECC,-- 9-bit ECC read address. Not used when RAM_MODE=TDP.SBITERR => SBITERR,-- 1-bit single bit error status outputADDRARDADDR => ADDRARDADDR, -- 16-bit A port address/Read address inputADDRBWRADDR => ADDRBWRADDR, -- 16-bit B port address/Write address inputCASCADEINA => CASCADEINA, -- 1-bit A port cascade inputCASCADEINB => CASCADEINB, -- 1-bit B port cascade inputCLKARDCLK => CLKARDCLK,-- 1-bit A port clock/Read clock inputCLKBWRCLK => CLKBWRCLK,-- 1-bit B port clock/Write clock inputDIADI => DIADI,-- 32-bit A port data/LSB data inputDIBDI => DIBDI,-- 32-bit B port data/MSB data inputDIPADIP => DIPADIP,-- 4-bit A port parity/LSB parity inputDIPBDIP => DIPBDIP,-- 4-bit B port parity/MSB parity inputENARDEN => ENARDEN,-- 1-bit A port enable/Read enable inputENBWREN => ENBWREN,-- 1-bit B port enable/Write enable inputINJECTDBITERR => INJECTDBITERR, -- 1-bit Inject a double bit error if ECC feature is used.INJECTSBITERR => INJECTSBITERR, -- 1-bit Inject a single bit error if ECC feature is used.REGCEAREGCE => REGCEAREGCE, -- 1-bit A port register enable/Register enable inputREGCEB => REGCEB,-- 1-bit B port register enable inputRSTRAMARSTRAM => RSTRAMARSTRAM, -- 1-bit A port set/reset inputRSTRAMB => RSTRAMB,-- 1-bit B port set/reset inputRSTREGARSTREG => RSTREGARSTREG, -- 1-bit A port register set/reset inputRSTREGB => RSTREGB,-- 1-bit B port register set/reset inputWEA => WEA,-- 4-bit A port write enable inputWEBWE => WEBWE-- 8-bit B port write enable/Write enable input);-- End of RAMB36E1_inst instantiation-- "WRITE_FIRST",-- "READ_FIRST", or-- "NO_CHANGE"-- "WRITE_FIRST",-- "READ_FIRST", or-- "NO_CHANGE"Verilog Instantiation Template// RAMB36E1: 36K-bit Configurable Synchronous Block RAM// Virtex-6// Xilinx HDL Language Template, version 11.1RAMB36E1 #(.DOA_REG(0),// Optional outputVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 297

Chapter 4: About Design Elements// register on A port// (0 or 1).DOB_REG(0),// Optional output// register on B port// (0 or 1).EN_ECC_READ("FALSE"),// Enable ECC decoder,// TRUE or FALSE.EN_ECC_WRITE("FALSE"),// Enable ECC encoder,// TRUE or FALSE// INITP_00 to INITP_0F: Allows specification of the initial contents of the 4KB parity data memory// array..INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_08(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_09(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_0F(256’h0000000000000000000000000000000000000000000000000000000000000000),// INIT_00 to INIT_7F: Allows specification of the initial contents of the 32KB data memory array..INIT_00(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_01(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_02(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_03(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_04(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_05(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_06(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_07(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_08(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_09(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_10(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_11(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_12(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_13(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_14(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_15(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_16(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_17(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_18(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_19(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_20(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_21(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_22(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_23(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_24(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_25(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_26(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_27(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_28(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_29(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2C(256’h0000000000000000000000000000000000000000000000000000000000000000),Virtex-6 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Chapter 4: About Design Elements.INIT_2D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_30(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_31(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_32(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_33(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_34(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_35(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_36(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_37(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_38(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_39(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_40(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_41(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_42(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_43(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_44(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_45(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_46(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_47(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_48(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_49(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_4F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_50(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_51(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_52(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_53(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_54(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_55(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_56(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_57(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_58(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_59(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_5F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_60(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_61(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_62(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_63(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_64(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_65(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_66(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_67(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_68(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_69(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_6F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_70(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_71(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_72(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_73(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_74(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_75(256’h0000000000000000000000000000000000000000000000000000000000000000),Virtex-6 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Chapter 4: About Design Elements.INIT_76(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_77(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_78(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_79(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_7F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_A(36’h000000000),// Initial values on A// output port.INIT_B(36’h000000000),// Initial values on B// output port.INIT_FILE("NONE"),// File name of file// used to specify// initial RAM// contents..RAM_EXTENSION_A("NONE"),// "UPPER", "LOWER", or// "NONE".RAM_EXTENSION_B("NONE"),// "UPPER", "LOWER", or// "NONE".RAM_MODE("TDP"),// SDP or TDP.READ_WIDTH_A(0), // 0, 1, 2, 4, 9, 18,// 36, or 72.READ_WIDTH_B(0), // 0, 1, 2, 4, 9, 18,// or 36.RSTREG_PRIORITY_A("RSTREG"),// RSTREG or REGCE.RSTREG_PRIORITY_B("RSTREG"),.SIM_COLLISION_CHECK("ALL"),.SRVAL_A(36’h000000000),.SRVAL_B(36’h000000000),// RSTREG or REGCE// Collision check// enable "ALL",// "WARNING_ONLY",// "GENERATE_X_ONLY" or// "NONE"// Set/Reset value for// A port output// Set/Reset value for// B port output.WRITE_WIDTH_A(0), // 0, 1, 2, 4, 9, 18,// or 36.WRITE_WIDTH_B(0), // 0, 1, 2, 4, 9, 18,// 36, or 72// WriteMode: Specifies output behavior of the port being written to: "WRITE_FIRST" = written value// appears on output port of the RAM "READ_FIRST" = previous RAM contents for that memory location appear// on the output port "NO_CHANGE" = previous value on the output port remains the same. Default is// WRITE_FIRST in TDP mode. Must equal READ_FIRST in SDP mode..WRITE_MODE_A("WRITE_FIRST"),.WRITE_MODE_B("WRITE_FIRST"))RAMB36E1_inst (.CASCADEOUTA(CASCADEOUTA),.CASCADEOUTB(CASCADEOUTB),.DBITERR(DBITERR),.DOADO(DOADO),.DOBDO(DOBDO),.DOPADOP(DOPADOP),.DOPBDOP(DOPBDOP),.ECCPARITY(ECCPARITY),.RDADDRECC(RDADDRECC),.SBITERR(SBITERR),.ADDRARDADDR(ADDRARDADDR),.ADDRBWRADDR(ADDRBWRADDR),.CASCADEINA(CASCADEINA),.CASCADEINB(CASCADEINB),.CLKARDCLK(CLKARDCLK),.CLKBWRCLK(CLKBWRCLK),.DIADI(DIADI),.DIBDI(DIBDI),.DIPADIP(DIPADIP),// 1-bit A port cascade output// 1-bit B port cascade output// 1-bit double bit error status output// 32-bit A port data/LSB data output// 32-bit B port data/MSB data output// 4-bit A port parity/LSB parity output// 4-bit B port parity/MSB parity output// 8-bit generated error correction parity// 9-bit ECC read address. Not used when RAM_MODE=TDP.// 1-bit single bit error status output// 16-bit A port address/Read address input// 16-bit B port address/Write address input// 1-bit A port cascade input// 1-bit B port cascade input// 1-bit A port clock/Read clock input// 1-bit B port clock/Write clock input// 32-bit A port data/LSB data input// 32-bit B port data/MSB data input// 4-bit A port parity/LSB parity input// "WRITE_FIRST",// "READ_FIRST", or// "NO_CHANGE"// "WRITE_FIRST",// "READ_FIRST", or// "NO_CHANGE"Virtex-6 Libraries Guide for HDL Designs300 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design Elements);.DIPBDIP(DIPBDIP),// 4-bit B port parity/MSB parity input.ENARDEN(ENARDEN),// 1-bit A port enable/Read enable input.ENBWREN(ENBWREN),// 1-bit B port enable/Write enable input.INJECTDBITERR(INJECTDBITERR), // 1-bit Inject a double bit error if ECC feature is used..INJECTSBITERR(INJECTSBITERR), // 1-bit Inject a single bit error if ECC feature is used..REGCEAREGCE(REGCEAREGCE), // 1-bit A port register enable/Register enable input.REGCEB(REGCEB),// 1-bit B port register enable input.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit A port set/reset input.RSTRAMB(RSTRAMB),// 1-bit B port set/reset input.RSTREGARSTREG(RSTREGARSTREG), // 1-bit A port register set/reset input.RSTREGB(RSTREGB),// 1-bit B port register set/reset input.WEA(WEA),// 4-bit A port write enable input.WEBWE(WEBWE)// 8-bit B port write enable/Write enable input// End of RAMB36E1_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 301

Chapter 4: About Design ElementsSRL16EPrimitive: 16-Bit Shift Register Look-Up Table (LUT) with Clock EnableIntroductionThis design element is a shift register look-up table (LUT). The inputs A3, A2, A1, and A0 select the outputlength of the shift register.The shift register can be of a fixed, static length or it can be dynamically adjusted.• To create a fixed-length shift register -Drive the A3 through A0 inputs with static values. The length ofthe shift register can vary from 1 bit to 16 bits, as determined by the following formula: Length = (8 x A3)+(4 x A2) + (2 x A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. Ifthey are all ones (1111), it is 16 bits long.• To change the length of the shift register dynamically -Change the values driving the A3 through A0inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), thelength of the shift register changes from 16 bits to 8 bits. Internally, the length of the shift register is always 16bits and the input lines A3 through A0 select which of the 16 bits reach the output.The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute.The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaultsto a value of four zeros (0000) so that the shift register LUT is cleared during configuration.When CE is High, the data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK)transition. During subsequent Low-to-High clock transitions, when CE is High, data shifts to the next highest bitposition as new data is loaded. The data appears on the Q output when the shift register length determined bythe address inputs is reached. When CE is Low, the register ignores clock transitions.Logic TableInputsOutputAm CE CLK D QAm 0 X X Q(Am)Am 1 ↑ D Q(Am - 1)m= 0, 1, 2, 3Virtex-6 Libraries Guide for HDL Designs302 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPort DescriptionsPort Direction Width FunctionQ Output 1 Shift register data outputD Input 1 Shift register data inputCLK Input 1 ClockCE Input 1 Active high clock enableA Input 4 Dynamic depth selection of the SRL• A=0000 ==> 1-bit shift length• A=1111 ==> 16-bit shift lengthDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINITHexadecimalAny 16-Bit Value All zeros Sets the initial value of content and output of shiftregister after configuration.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock-- All FPGAs-- Xilinx HDL Libraries Guide, version 11.2SRL16E_inst : SRL16Egeneric map (INIT => X"0000")port map (Q => Q, -- SRL data outputA0 => A0, -- Select[0] inputA1 => A1, -- Select[1] inputA2 => A2, -- Select[2] inputA3 => A3, -- Select[3] inputCE => CE, -- Clock enable inputCLK => CLK, -- Clock inputD => D -- SRL data input);-- End of SRL16E_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 303

Chapter 4: About Design ElementsVerilog Instantiation Template// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock// All FPGAs// Xilinx HDL Libraries Guide, version 11.2SRL16E #(.INIT(16’h0000) // Initial Value of Shift Register) SRL16E_inst (.Q(Q), // SRL data output.A0(A0), // Select[0] input.A1(A1), // Select[1] input.A2(A2), // Select[2] input.A3(A3), // Select[3] input.CE(CE), // Clock enable input.CLK(CLK), // Clock input.D(D) // SRL data input);// End of SRL16E_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs304 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsSRLC32EPrimitive: 32 Clock Cycle, Variable Length Shift Register Look-Up Table (LUT) with Clock EnableIntroductionThis design element is a variable length, 1 to 32 clock cycle shift register implemented within a single look-uptable (LUT). The shift register can be of a fixed length, static length, or it can be dynamically adjusted by changingthe address lines to the component. This element also features an active, high-clock enable and a cascadingfeature in which multiple SRLC32Es can be cascaded in order to create greater shift lengths.Port DescriptionsPort Direction Width FunctionQ Output 1 Shift register data outputQ31 Output 1 Shift register cascaded output (connect to the D inputof a subsequent SRLC32E)D Input 1 Shift register data inputCLK Input 1 ClockCE Input 1 Active high clock enableA Input 5 Dynamic depth selection of the SRLA=00000 ==> 1-bit shift lengthA=11111 ==> 32-bit shift lengthVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 305

Chapter 4: About Design ElementsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoIf instantiated, the following connections should be made to this component:• Connect the CLK input to the desired clock source, the D input to the data source to be shifted/stored and theQ output to either an FDCPE or an FDRSE input or other appropriate data destination.• The CE clock enable pin can be connected to a clock enable signal in the design or else tied to a logic oneif not used.• The 5-bit A bus can either be tied to a static value between 0 and 31 to signify a fixed 1 to 32 bit static shiftlength, or else it can be tied to the appropriate logic to enable a varying shift depth anywhere between 1and 32 bits.• If you want to create a longer shift length than 32, connect the Q31 output pin to the D input pin of asubsequent SRLC32E to cascade and create larger shift registers.• It is not valid to connect the Q31 output to anything other than another SRLC32E.• The selectable Q output is still available in the cascaded mode, if needed.• An optional INIT attribute consisting of a 32-bit Hexadecimal value can be specified to indicate the initialshift pattern of the shift register.• (INIT[0] will be the first value shifted out.)Available AttributesAttribute Type Allowed Values Default DescriptionINITHexadecimalAny 32-Bit Value All zeros Specifies the initial shift pattern of theSRLC32E.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- SRLC32E: 32-bit variable length shift register LUT-- with clock enable-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2SRLC32E_inst : SRLC32Egeneric map (INIT => X"00000000")port map (Q => Q, -- SRL data outputQ31 => Q31, -- SRL cascade output pinA => A, -- 5-bit shift depth select inputCE => CE, -- Clock enable inputCLK => CLK, -- Clock inputD => D-- SRL data input);-- End of SRLC32E_inst instantiationVirtex-6 Libraries Guide for HDL Designs306 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// SRLC32E: 32-bit variable length shift register LUT// with clock enable// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2SRLC32E #(.INIT(32’h00000000) // Initial Value of Shift Register) SRLC32E_inst (.Q(Q), // SRL data output.Q31(Q31), // SRL cascade output pin.A(A), // 5-bit shift depth select input.CE(CE), // Clock enable input.CLK(CLK), // Clock input.D(D) // SRL data input);// End of SRLC32E_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 307

Chapter 4: About Design ElementsSTARTUP_VIRTEX6Primitive: Virtex®-6 Configuration Start-Up Sequence InterfaceIntroductionThis design element is used to interface device pins and logic to the Global Set/Reset (GSR) signal, the GlobalTristate (GTS) dedicated routing, the internal configuration signals, or the input pins for the SPI PROM ifan SPI PROM is used to configure the device. This primitive can also be used to specify a different clock forthe device startup sequence at the End of Configuring of the device, and to access the configuration clock tothe internal logic.Virtex-6 Libraries Guide for HDL Designs308 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPort DescriptionsPort Type Width FunctionCFGCLK Output 1 Configuration main clock output.CFGMCLK Output 1 Configuration internal oscillator clock output.CLK Input 1 User startup clock.DINSPI Output 1 Internal access to the DIN configuration pin when usingSPI PROM configurationEOS Output 1 Active High signal indicates the End Of Configuration.GSR Input 1 Active High Global Set/Reset (GSR) signal.GTS Input 1 Active High Global Tristate (GTS) signal.KEYCLEARB Input 1 Clear AES Decrypter Key from Battery-Backed RAM(BBRAM). To erase the battery-backed-RAM contents, pullKEYCLEARB Low for more than ~200ns.PACK Input 1 PROGRAM acknowledge.PREQ Output 1 PROGRAM request to fabricTCKSPI Output 1 Internal access to the TCK configuration pin when usingSPI PROM configuration.USRCCLKO Input 1 Internal user CCLK.USRCCLKTS Input 1 Internal user CCLK tristate enable.USRDONEO Input 1 Internal user DONE pin output controlUSRDONETS Input 1 User DONE tristate enableDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoIf the dedicated global tristate is to be used, connect the appropriate sourcing pin or logic to the GTS input pin ofthe primitive. To specify a clock for the startup sequence of configuration, connect a clock from the design to theCLK pin of this design element. CFGMCLK and CFGCLK allow access to the internal configuration clocks, whileEOS signals the end of the configuration startup sequence.If you are configuring the device using a SPI PROM, and access to the SPI PROM is necessary after configuration,use the TCK_SPI and DIN_SPI pins of the component to gain access to the otherwise dedicated configurationinput pins.Available AttributesAttribute Type Allowed Values Default DescriptionPROG_USR Boolean FALSE, TRUE FALSE Activate program event security featureCFGCLK_EN Boolean FALSE, TRUE FALSE Enables the Configuration logic main clock.CFGMCLK_EN Boolean FALSE, TRUE FALSE Enables the Configuration internal oscillatorclock .Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 309

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- STARTUP_VIRTEX6: Virtex-6 Configuration Start-Up Sequence Interface-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2STARTUP_VIRTEX6_inst : STARTUP_VIRTEX6generic map (PROG_USR => FALSE -- Activate program event security feature)port map (CFGCLK => CFGCLK, -- 1-bit Configuration main clock outputCFGMCLK => CFGMCLK, -- 1-bit Configuration internal oscillator clock outputDINSPI => DINSPI, -- 1-bit Internal access to the DIN configuration pin when using SPI PROM-- configurationEOS => EOS,PREQ => PREQ,TCKSPI => TCKSPI,-- 1-bit Active high signal indicates the End Of Configuration.-- 1-bit PROGRAM request to fabric-- 1-bit Internal access to the TCK configuration pin when using SPI PROM-- configurationCLK => CLK,-- 1-bit User start-up clockGSR => GSR,-- 1-bit Active high Global Set/Reset signalGTS => GTS,-- 1-bit Active high Global 3-State signalKEYCLEARB => KEYCLEARB, -- 1-bit Clear AES Decrypter Key from Battery-Backed RAM (BBRAM). To erase the-- battery-backed-RAM contents, pull KEYCLEARB low for more than ~200ns.);PACK => PACK,-- 1-bit PROGRAM acknowledgeUSRCCLKO => USRCCLKO, -- 1-bit Internal user CCLKUSRCCLKTS => USRCCLKTS, -- 1-bit Internal user CCLK 3-state enableUSRDONEO => USRDONEO, -- 1-bit Internal user DONE pin output controlUSRDONETS => USRDONETS -- 1-bit User DONE 3-state enable-- End of STARTUP_VIRTEX6_inst instantiationVirtex-6 Libraries Guide for HDL Designs310 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVerilog Instantiation Template// STARTUP_VIRTEX6: Virtex-6 Configuration Start-Up Sequence Interface// Virtex-6// Xilinx HDL Language Template, version 11.1STARTUP_VIRTEX6 #(.PROG_USR("FALSE") // Activate program event security feature)STARTUP_VIRTEX6_inst (.CFGCLK(CFGCLK), // 1-bit Configuration main clock output.CFGMCLK(CFGMCLK), // 1-bit Configuration internal oscillator clock output.DINSPI(DINSPI), // 1-bit Internal access to the DIN configuration pin when using SPI PROM// configuration.EOS(EOS),.PREQ(PREQ),.TCKSPI(TCKSPI),// 1-bit Active high signal indicates the End Of Configuration.// 1-bit PROGRAM request to fabric// 1-bit Internal access to the TCK configuration pin when using SPI PROM// configuration.CLK(CLK),// 1-bit User start-up clock.GSR(GSR),// 1-bit Active high Global Set/Reset signal.GTS(GTS),// 1-bit Active high Global 3-State signal.KEYCLEARB(KEYCLEARB), // 1-bit Clear AES Decrypter Key from Battery-Backed RAM (BBRAM). To erase the// battery-backed-RAM contents, pull KEYCLEARB low for more than ~200ns.);.PACK(PACK),// 1-bit PROGRAM acknowledge.USRCCLKO(USRCCLKO), // 1-bit Internal user CCLK.USRCCLKTS(USRCCLKTS), // 1-bit Internal user CCLK 3-state enable.USRDONEO(USRDONEO), // 1-bit Internal user DONE pin output control.USRDONETS(USRDONETS) // 1-bit User DONE 3-state enable// End of STARTUP_VIRTEX6_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 311

Chapter 4: About Design ElementsSYSMONPrimitive: System MonitorIntroductionThis design element is built around a 10-bit, 200-kSPS (kilosamples per second) Analog-to-Digital Converter(ADC). When combined with a number of on-chip sensors, the ADC is used to measure FPGA physical operatingparameters, including on-chip power supply voltages and die temperatures. Access to external voltages isprovided through a dedicated analog-input pair (VP/VN) and 16 user-selectable analog inputs, known asauxiliary analog inputs (VAUXP[15:0], VAUXN[15:0]). The external analog inputs allow the ADC to monitorthe physical environment of the board or enclosure.Port DescriptionsPort Type Width FunctionALM[2:0] Output 3 3-bit output alarm for temp, Vccint and VccauxBUSY Output 1 1-bit output ADC busy signalCHANNEL[4:0] Output 5 5-bit output channel selectionCONVST Input 1 1-bit input convert startCONVSTCLK Input 1 1-bit input convert start clockDADDR[6:0] Input 7 7-bit input address bus for dynamic reconfigDCLK Input 1 1-bit input clock for dynamic reconfigDEN Input 1 1-bit input enable for dynamic reconfigDI[15:0] Input 16 16-bit input data bus for dynamic reconfigDO[15:0] Output 16 16-bit output data bus for dynamic reconfigDRDY Output 1 1-bit output data ready for dynamic reconfigDWE Input 1 1-bit input write enable for dynamic reconfigEOC Output 1 1-bit output end of conversionEOS Output 1 1-bit output end of sequenceJTAGBUSY Output 1 1-bit output JTAG DRP busyJTAGLOCKED Output 1 1-bit output DRP port lockVirtex-6 Libraries Guide for HDL Designs312 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsPort Type Width FunctionJTAGMODIFIED Output 1 1-bit output JTAG write to DRPOT Output 1 1-bit output over temperature alarmRESET Input 1 1-bit input active high resetVAUXN[15:0] Input 16 16-bit input N-side auxiliary analog inputVAUXP[15:0] Input 16 16-bit input P-side auxiliary analog inputVN Input 1 1-bit input N-side analog inputVP Input 1 1-bit input P-side analog inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoNoConnect all desired input and output ports and set the appropriate attributes for the desired behavior of thiscomponent. For simulation, provide a text file to give the analog and temperature to the model. The formatfor this file is as follows:// Must use valid headers on all columns// Comments can be added to the stimulus file using ’//’TIME TEMP VCCAUX VCCINT VP VN VAUXP[0] VAUXN[0]00000 45 2.5 1.0 0.5 0.0 0.7 0.005000 85 2.45 1.1 0.3 0.0 0.2 0.0// Time stamp data is in nano seconds (ns)// Temperature is recorded in C (degrees centigrade)// All other channels are recorded as V (Volts)// Valid column headers are:// TIME, TEMP, VCCAUX, VCCINT, VP, VN,// VAUXP[0], VAUXN[0],...............VAUXP[15], VAUXN[15]// External analog inputs are differential so VP = 0.5 and VN = 0.0 the// input on channel VP/VN is 0.5 - 0.0 = 0.5VNote When compiling the included code, please do not add any extraneous spaces to the text as this couldcause compilation to fail.Available AttributesAttribute Type Allowed_ValuesDefault DescriptionINIT_40INIT_41INIT_42INIT_43INIT_44INIT_45HexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimal16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 Configuration register 016’h0000 Configuration register 116’h0800 Configuration register 216’h0000 Test register 016’h0000 Test register 116’h0000 Test register 2Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 313

Chapter 4: About Design ElementsAttribute Type Allowed_ValuesDefault DescriptionINIT_46INIT_47INIT_48INIT_49INIT_4AINIT_4BINIT_4CINIT_4DINIT_4EINIT_4FINIT_50INIT_51INIT_52INIT_53INIT_54INIT_55INIT_56INIT_57HexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimal16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffffSIM_DEVICE String “VIRTEX5”,”VIRTEX6”16’h0000 Test register 316’h0000 Test register 416’h0000 Sequence register 016’h0000 Sequence register 116’h0000 Sequence register 216’h0000 Sequence register 316’h0000 Sequence register 416’h0000 Sequence register 516’h0000 Sequence register 616’h0000 Sequence register 716’h0000 Alarm limit register 016’h0000 Alarm limit register 116’h0000 Alarm limit register 216’h0000 Alarm limit register 316’h0000 Alarm limit register 416’h0000 Alarm limit register 516’h0000 Alarm limit register 616’h0000 Alarm limit register 7“VIRTEX5”Allows the simulation model to reflect thereduction of the minimum divide ratio betweenthe DRP clock (DCLK) and the lower frequencyADC clock (ADCCLOCK) from 8 to 2.SIM_MONITOR_FILE String 0 bit String design.txt Simulation analog entry fileVirtex-6 Libraries Guide for HDL Designs314 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- SYSMON: System Monitor-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2SYSMON_inst : SYSMONgeneric map (INIT_40 => X"0000", -- Configuration register 0INIT_41 => X"0000", -- Configuration register 1INIT_42 => X"0800", -- Configuration register 2INIT_43 => X"0000", -- Test register 0INIT_44 => X"0000", -- Test register 1INIT_45 => X"0000", -- Test register 2INIT_46 => X"0000", -- Test register 3INIT_47 => X"0000", -- Test register 4INIT_48 => X"0000", -- Sequence register 0INIT_49 => X"0000", -- Sequence register 1INIT_4A => X"0000", -- Sequence register 2INIT_4B => X"0000", -- Sequence register 3INIT_4C => X"0000", -- Sequence register 4INIT_4D => X"0000", -- Sequence register 5INIT_4E => X"0000", -- Sequence register 6INIT_4F => X"0000", -- Sequence register 7INIT_50 => X"0000", -- Alarm limit register 0INIT_51 => X"0000", -- Alarm limit register 1INIT_52 => X"0000", -- Alarm limit register 2INIT_53 => X"0000", -- Alarm limit register 3INIT_54 => X"0000", -- Alarm limit register 4INIT_55 => X"0000", -- Alarm limit register 5INIT_56 => X"0000", -- Alarm limit register 6INIT_57 => X"0000", -- Alarm limit register 7SIM_DEVICE => "VIRTEX5",-- Device family selectionSIM_MONITOR_FILE => "design.txt"-- Simulation analog entry file)port map (ALM => ALM,-- 3-bit output alarm for temp, Vccint and VccauxBUSY => BUSY,-- 1-bit output ADC busy signalCHANNEL => CHANNEL,-- 5-bit output channel selectionDO => DO,-- 16-bit output data bus for dynamic reconfigDRDY => DRDY,-- 1-bit output data ready for dynamic reconfigEOC => EOC,-- 1-bit output end of conversionEOS => EOS,-- 1-bit output end of sequenceJTAGBUSY => JTAGBUSY,-- 1-bit output JTAG DRP busyJTAGLOCKED => JTAGLOCKED, -- 1-bit output DRP port lockJTAGMODIFIED => JTAGMODIFIED, -- 1-bit output JTAG write to DRPOT => OT,-- 1-bit output over temperature alarmCONVST => CONVST,-- 1-bit input convert startCONVSTCLK => CONVSTCLK, -- 1-bit input convert start clockDADDR => DADDR,-- 7-bit input address bus for dynamic reconfigDCLK => DCLK,-- 1-bit input clock for dynamic reconfigDEN => DEN,-- 1-bit input enable for dynamic reconfigDI => DI,-- 16-bit input data bus for dynamic reconfigDWE => DWE,-- 1-bit input write enable for dynamic reconfigRESET => RESET,-- 1-bit input active high resetVAUXN => VAUXN,-- 16-bit input N-side auxiliary analog inputVAUXP => VAUXP,-- 16-bit input P-side auxiliary analog inputVN => VN,-- 1-bit input N-side analog inputVP => VP-- 1-bit input P-side analog input);-- End of SYSMON_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 315

Chapter 4: About Design ElementsVerilog Instantiation Template// SYSMON: System Monitor// Virtex-5, Virtex-6// Xilinx HDL Libraries Guide, version 11.2SYSMON #(.INIT_40(16’h0), // Configuration register 0.INIT_41(16’h0), // Configuration register 1.INIT_42(16’h0), // Configuration register 2.INIT_43(16’h0), // Test register 0.INIT_44(16’h0), // Test register 1.INIT_45(16’h0), // Test register 2.INIT_46(16’h0), // Test register 3.INIT_47(16’h0), // Test register 4.INIT_48(16’h0), // Sequence register 0.INIT_49(16’h0), // Sequence register 1.INIT_4A(16’h0), // Sequence register 2.INIT_4B(16’h0), // Sequence register 3.INIT_4C(16’h0), // Sequence register 4.INIT_4D(16’h0), // Sequence register 5.INIT_4E(16’h0), // Sequence register 6.INIT_4F(16’h0), // Sequence register 7.INIT_50(16’h0), // Alarm limit register 0.INIT_51(16’h0), // Alarm limit register 1.INIT_52(16’h0), // Alarm limit register 2.INIT_53(16’h0), // Alarm limit register 3.INIT_54(16’h0), // Alarm limit register 4.INIT_55(16’h0), // Alarm limit register 5.INIT_56(16’h0), // Alarm limit register 6.INIT_57(16’h0), // Alarm limit register 7.SIM_MONITOR_FILE("design.txt") // Simulation analog entry file) SYSMON_inst (.ALM(ALM),// 3-bit output for temp, Vccint and Vccaux.BUSY(BUSY),// 1-bit output ADC busy signal.CHANNEL(CHANNEL), // 5-bit output channel selection.DO(DO),// 16-bit output data bus for dynamic reconfig.DRDY(DRDY),// 1-bit output data ready for dynamic reconfig.EOC(EOC),// 1-bit output end of conversion.EOS(EOS),// 1-bit output end of sequence.JTAGBUSY(JTAGBUSY), // 1-bit output JTAG DRP busy.JTAGLOCKED(JTAGLOCKED), // 1-bit output DRP port lock.JTAGMODIFIED(JTAGMODIFIED), // 1-bit output JTAG write to DRP.OT(OT),// 1-bit output over temperature alarm.CONVST(CONVST), // 1-bit input convert start.CONVSTCLK(CONVSTCLK), // 1-bit input convert start clock.DADDR(DADDR), // 7-bit input address bus for dynamic reconfig.DCLK(DCLK),// 1-bit input clock for dynamic reconfig.DEN(DEN),// 1-bit input enable for dynamic reconfig.DI(DI),// 16-bit input data bus for dynamic reconfig.DWE(DWE),// 1-bit input write enable for dynamic reconfig.RESET(RESET), // 1-bit input active high reset.VAUXN(VAUXN), // 16-bit input N-side auxiliary analog input.VAUXP(VAUXP), // 16-bit input P-side auxiliary analog input.VN(VN),// 1-bit input N-side analog input.VP(VP)// 1-bit input P-side analog input);// End of SYSMON_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs316 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsTEMAC_SINGLEPrimitive: Tri-mode Ethernet Media Access Controller (MAC)IntroductionThe TEMAC_SINGLE library primitive provides the ports and attributes necessary to instantiate the Virtex®-6FPGA Embedded Tri-Mode Ethernet MAC. Because it encompasses SecureIP encrypted HDL, it is also used forfunctional and timing simulations. This primitive can be simplified for specific customer needs by using theCORE Generator tool to create Ethernet MAC wrappersVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 317

Chapter 4: About Design ElementsDesign Entry MethodTo instantiate this component, use the Embedded Development Kit (EDK) or an associated core containing thecomponent. Xilinx does not recommend direct instantiation of this component.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs318 www.xilinx.com UG623 (v 11.4) December 2, 2009

Chapter 4: About Design ElementsUSR_ACCESS_VIRTEX6Primitive: Virtex-6 User Access RegisterIntroductionThis design element enables access to a 32-bit register within the configuration logic. You will thus be able toread the data from the bitstream. One use for this component is to allow data stored in bitstream storage sourceto be accessed by the FPGA design after configuration.Port DescriptionsPort Type Width FunctionCFGCLK Output 1 Configuration ClockDATA[31:0] Output 32 Configuration Output DataDATAVALID Output 1 Active high DATA port contains valid dataDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- USR_ACCESS_VIRTEX6: Virtex-6 User Access Register-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2USR_ACCESS_VIRTEX6_inst : USR_ACCESS_VIRTEX6generic map ()port map (CFGCLK => CFGCLK, -- 1-bit Configuration ClockDATA => DATA,-- 32-bit Configuration Output DataDATAVALID => DATAVALID -- 1-bit Active high DATA port contains valid data);-- End of USR_ACCESS_VIRTEX6_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 319

Chapter 4: About Design ElementsVerilog Instantiation Template// USR_ACCESS_VIRTEX6: Virtex-6 User Access Register// Virtex-6// Xilinx HDL Language Template, version 11.1USR_ACCESS_VIRTEX6 USR_ACCESS_VIRTEX6_inst (.CFGCLK(CFGCLK), // 1-bit Configuration Clock.DATA(DATA),// 32-bit Configuration Output Data.DATAVALID(DATAVALID) // 1-bit Active high DATA port contains valid data);// End of USR_ACCESS_VIRTEX6_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs320 www.xilinx.com UG623 (v 11.4) December 2, 2009