Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About UnimacrosFIFO_SYNC_MACROMacro: Synchronous First-In, First-Out (FIFO) RAM BufferIntroductionFPGA devices contain several block RAM memories that can be configured as general-purpose 36kb or 18kbRAM/ROM memories. Dedicated logic in the block RAM enables you to easily implement FIFOs. The FIFOcan be configured as an 18 kb or 36 kb memory. This unimacro configures the FIFO such that it uses one clockfor reading as well as writing.Port DescriptionName Direction Width FunctionOutput PortsALMOSTEMPTY Output 1 Almost all valid entries in FIFO have been read.ALMOSTFULL Output 1 Almost all entries in FIFO memory have beenfilled.DO Output See ConfigurationTable.EMPTY Output 1 FIFO is empty.Data output bus addressed by ADDR.FULL Output 1 All entries in FIFO memory are filled.RDCOUNT Output See ConfigurationTable below.FIFO data read pointer.RDERR Output 1 When the FIFO is empty, any additional readoperation generates an error flag.WRCOUNT Output See ConfigurationTable.FIFO data write pointer.Virtex-6 Libraries Guide for HDL Designs50 www.xilinx.com UG623 (v 11.4) December 2, 2009