Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsBUFGConvenience Primitive: Global Clock BufferIntroductionThis design element is a high-fanout buffer that connects signals to the global routing resources for low skewdistribution of the signal. BUFGs are typically used on clock nets.Port DescriptionsPort Type Width FunctionI Input 1 Clock buffer outputO Output 1 Clock buffer inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- BUFG: Global Clock Buffer-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2BUFG_inst : BUFGgeneric map ()port map (O => O, -- 1-bit Clock buffer outputI => I -- 1-bit Clock buffer input);-- End of BUFG_inst instantiationVirtex-6 Libraries Guide for HDL Designs86 www.xilinx.com UG623 (v 11.4) December 2, 2009