Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsPort DescriptionsPort Direction Width FunctionDOA Output 2 Read port data outputs addressed by ADDRADOB Output 2 Read port data outputs addressed by ADDRBDOC Output 2 Read port data outputs addressed by ADDRCDOD Output 2 Read/Write port data outputs addressed by ADDRDDIA Input 2 Write data inputs addressed by ADDRD (read output isaddressed by ADDRA)DIB Input 2 Write data inputs addressed by ADDRD (read output isaddressed by ADDRB)DIC Input 2 Write data inputs addressed by ADDRD (read output isaddressed by ADDRC)DID Input 2 Write data inputs addressed by ADDRDADDRA Input 5 Read address bus AADDRB Input 5 Read address bus BADDRC Input 5 Read address bus CADDRD Input 5 8-bit data write port, 2-bit data read port address bus DWE Input 1 Write EnableWCLK Input 1 Write clock (reads are asynchronous)Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoThis element can be inferred by some synthesis tools by describing a RAM with a synchronous write andasynchronous read capability. Consult your synthesis tool documentation for details on RAM inferencecapabilities and coding examples. Xilinx suggests that you instantiate RAM32Ms if you have a need to implicitlyspecify the RAM function, or if you need to manually place or relationally place the component. If a synchronousread capability is desired, the RAM32M outputs can be connected to an FDRSE (FDCPE is asynchronous set/resetis necessary) in order to improve the output timing of the function. However, this is not necessary for theproper operation of the RAM.If you want to have the data clocked on the negative edge of a clock, an inverter can be described on the clockinput to this component. This inverter will be absorbed into the block, giving you the ability to write to the RAMon falling clock edges.If instantiated, the following connections should be made to this component. Tie the WCLK input to the desiredclock source, the DIA, DIB, DIC and DID inputs to the data source to be stored and the DOA, DOB, DOC andDOD outputs to an FDCE D input or other appropriate data destination or left unconnected if not used. The WEclock enable pin should be connected to the proper write enable source in the design. The 5-bit ADDRD busshould be connected to the source for the read/write addressing and the 5-bit ADDRA, ADDRB and ADDRCbuses should be connected to the appropriate read address connections. The optional INIT_A, INIT_B, INIT_Cand INIT_D attributes consisting of a 64-bit hexadecimal values that specifies each port’s initial memory contentscan be specified. The INIT value correlates to the RAM addressing by the following equation: ADDRy[z] =INIT_y[2*z+1:2*z]. For instance, if the RAM ADDRC port is addressed to 00001, then the INIT_C[3:2] valueswould be the initial values shown on the DOC port before the first write occurs at that address. If left unspecified,the initial contents will default to all zeros.Virtex-6 Libraries Guide for HDL Designs266 www.xilinx.com UG623 (v 11.4) December 2, 2009