Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsIBUFDS_GTHE1Primitive: Differential Clock Input for the GTH Transceiver Reference ClocksIntroductionThis component is the dedicated differential clock input for the GTH transceiver reference clocks. There is oneIBUFGDS_GTHE1 component per GTH quad and it connects directly to the REFCLK pin of the GTHE1_QUADprimitive.Design Entry MethodTo instantiate this component, use the Virtex-6 FPGA GTH Transceivers Wizard or an associated core containingthe component. Xilinx does not recommend direct instantiation of this component.For More Information• See the Virtex-6 FPGA GTH Transceivers User Guide.• See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs156 www.xilinx.com UG623 (v 11.4) December 2, 2009