Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsPort Direction Width FunctionR Input 1 Active high reset forcing Q1 and Q2 to a logic zero. Canbe synchronous or asynchronous based on the SRTYPEattribute.S Input 1 Active high reset forcing Q1 and Q2 to a logic one. Canbe synchronous or asynchronous based on the SRTYPEattribute.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNo• Connect the C pin to the appropriate clock source, representing the positive clock edge and CB to theclock source representing the negative clock edge.• Connect the D pin to the top-level input, or bidirectional port, an IODELAY, or an instantiated inputor bidirectional buffer.• The Q1 and Q2 pins should be connected to the appropriate data sources.• CE should be tied high when not used, or connected to the appropriate clock enable logic.• R and S pins should be tied low, if not used, or to the appropriate set or reset generation logic.• Set all attributes to the component to represent the desired behavior.• Always instantiate this component in pairs with the same clocking, and to LOC those to the appropriate Pand N I/O pair in order not to sacrifice possible I/O resources.• Always instantiate this component in the top-level hierarchy of your design, along with any otherinstantiated I/O components for the design. This helps facilitate hierarchical design flows/practices.• To minimize CLK skew, both CLK and CLKB should come from global routing (DCM / MMCM) and notfrom the local inversion. DCM / MMCM de-skews these clocks whereas the local inversion adds skew.Available AttributesAttribute Type Allowed Values Default DescriptionDDR_CLK_EDGE String"OPPOSITE_EDGE","SAME_EDGE""SAME_EDGE_PIPELINED""OPPOSITE_EDGE”DDR clock mode recovery modeselection. See Introduction for moreexplanation.INIT_Q1 Binary 0, 1 0 Initial value on the Q1 pin afterconfiguration startup or when GSR isasserted.INIT_Q2 Binary 0, 1 0 Initial value on the Q2 pin afterconfiguration startup or when GSR isasserted.SRTYPE String "SYNC" or "ASYNC” "SYNC” Set/reset type selection. SYNC"specifies the behavior of the reset (R)and set (S) pins to be synchronous tothe positive edge of the C clock pin."ASYNC" specifies an asynchronousset/reset function.Virtex-6 Libraries Guide for HDL Designs168 www.xilinx.com UG623 (v 11.4) December 2, 2009