Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionCLK_SEL_TYPE String “SYNC”, “ASYNC” “SYNC” Specifies synchronous or asynchronousclock.DISABLE_VALUE String “HIGH”, “LOW” “LOW” Specifies the state the output assumeswhen switching between inputs.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- BUFGMUX: Global Clock MUX Buffer-- Spartan-6-- Xilinx HDL Libraries Guide, version 11.2BUFGMUX_inst : BUFGMUXgeneric map (CLK_SEL_TYPE => "SYNC",)port map (O => O, -- 1-bit Clock MUX outputI0 => I0, -- 1-bit Clock0 inputI1 => I1, -- 1-bit Clock1 inputS => S -- 1-bit Clock select input);-- End of BUFGMUX_inst instantiationVerilog Instantiation Template// BUFGMUX: Global Clock Buffer 2-to-1 MUX// Spartan-3/3E/3A/6// Xilinx HDL Libraries Guide, version 11.2BUFGMUX BUFGMUX_inst (.O(O), // Clock MUX output.I0(I0), // Clock0 input.I1(I1), // Clock1 input.S(S) // Clock select input);// End of BUFGMUX_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 95