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Xilinx Virtex-6 Libraries Guide for HDL Designs

Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 4: About Design ElementsPort Type Width FunctionJTAGMODIFIED Output 1 1-bit output JTAG write to DRPOT Output 1 1-bit output over temperature alarmRESET Input 1 1-bit input active high resetVAUXN[15:0] Input 16 16-bit input N-side auxiliary analog inputVAUXP[15:0] Input 16 16-bit input P-side auxiliary analog inputVN Input 1 1-bit input N-side analog inputVP Input 1 1-bit input P-side analog inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoNoConnect all desired input and output ports and set the appropriate attributes <strong>for</strong> the desired behavior of thiscomponent. For simulation, provide a text file to give the analog and temperature to the model. The <strong>for</strong>mat<strong>for</strong> this file is as follows:// Must use valid headers on all columns// Comments can be added to the stimulus file using ’//’TIME TEMP VCCAUX VCCINT VP VN VAUXP[0] VAUXN[0]00000 45 2.5 1.0 0.5 0.0 0.7 0.005000 85 2.45 1.1 0.3 0.0 0.2 0.0// Time stamp data is in nano seconds (ns)// Temperature is recorded in C (degrees centigrade)// All other channels are recorded as V (Volts)// Valid column headers are:// TIME, TEMP, VCCAUX, VCCINT, VP, VN,// VAUXP[0], VAUXN[0],...............VAUXP[15], VAUXN[15]// External analog inputs are differential so VP = 0.5 and VN = 0.0 the// input on channel VP/VN is 0.5 - 0.0 = 0.5VNote When compiling the included code, please do not add any extraneous spaces to the text as this couldcause compilation to fail.Available AttributesAttribute Type Allowed_ValuesDefault DescriptionINIT_40INIT_41INIT_42INIT_43INIT_44INIT_45HexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimal16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 Configuration register 016’h0000 Configuration register 116’h0800 Configuration register 216’h0000 Test register 016’h0000 Test register 116’h0000 Test register 2<strong>Virtex</strong>-6 <strong>Libraries</strong> <strong>Guide</strong> <strong>for</strong> <strong>HDL</strong> <strong>Designs</strong>UG623 (v 11.4) December 2, 2009 www.xilinx.com 313

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