Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About UnimacrosADDMACC_MACROMacro: Adder/Multiplier/AccumulatorIntroductionThe ADDMACC _MACRO simplifies the instantiation of the DSP48 block when used as a pre-add, multiplyaccumulate function. It features parameterizable input and output widths and latency that ease the integration ofDSP48 block into HDL.Port DescriptionName Direction Width FunctionOutput PortsPRODUCT Output Variable width, equals the valueof the WIDTH_A attibute plus thevalue of the WIDTH_B attribute.Input PortsPREADD1 Input Variable, see WIDTH_PREADDattribute.PREADD2 Input Variable, see WIDTH_PREADDattribute.MULTIPLIER Input Variable, seeWIDTH_MULTIPLIER attribute.Primary data output.Preadder data input.Preadder data inputMultiplier data inputCARRYIN Input 1 Carry inputCLK Input 1 ClockCE Inupt 1 Clock enableLOAD Input 1 LoadLOAD_DATA Input Variable, see WIDTH_PRODUCTattribute.RST Input 1 Synchronous ResetIn a DSP slice, when LOAD is asserted, loads Pwith A*B+LOAD_DATA.Virtex-6 Libraries Guide for HDL Designs54 www.xilinx.com UG623 (v 11.4) December 2, 2009