Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 4: About Design Elements.CLKOUT1_DIVIDE(1), // Counter divide value.CLKOUT1_DUTY_CYCLE(0.5), // Counter output duty cycle.CLKOUT1_PHASE(0.0), // Counter output phase relative to the output clock.CLKOUT2_DIVIDE(1), // Counter divide value.CLKOUT2_DUTY_CYCLE(0.5), // Counter output duty cycle.CLKOUT2_PHASE(0.0), // Counter output phase relative to the output clock.CLKOUT3_DIVIDE(1), // Counter divide value.CLKOUT3_DUTY_CYCLE(0.5), // Counter output duty cycle.CLKOUT3_PHASE(0.0), // Counter output phase relative to the output clock.CLKOUT4_CASCADE("FALSE"),.CLKOUT4_DIVIDE(1), // Counter divide value.CLKOUT4_DUTY_CYCLE(0.5), // Counter output duty cycle.CLKOUT4_PHASE(0.0), // Counter output phase relative to the output clock.CLKOUT5_DIVIDE(1), // Counter divide value.CLKOUT5_DUTY_CYCLE(0.5), // Counter output duty cycle.CLKOUT5_PHASE(0.0), // Counter output phase relative to the output clock.CLKOUT6_DIVIDE(1), // Counter divide value.CLKOUT6_DUTY_CYCLE(0.5), // Counter output duty cycle.CLKOUT6_PHASE(0.0), // Counter output phase relative to the output clock.CLOCK_HOLD("FALSE"),.DIVCLK_DIVIDE(1),// Counter divide value, always configured for 50% duty cycle.REF_JITTER1(0.0),// The reference clock2 jitter is specified in terms of the UI which is a// percentage of the reference clock. The number provided should be the// maximum peak to peak value our part can expect on the input clock. Default// is 0.1UI. This parameter should support out to three decimal places..STARTUP_WAIT("FALSE") // When TRUE, the MMCM locks before DONE goes high)MMCM_BASE_inst (.CLKFBOUT(CLKFBOUT), // 1-bit MMCM Feedback clock output.CLKFBOUTB(CLKFBOUTB), // 1-bit Inverted MMCM feedback clock output.CLKOUT0(CLKOUT0), // 1-bit MMCM clock output 0.CLKOUT0B(CLKOUT0B), // 1-bit Inverted MMCM clock output 0.CLKOUT1(CLKOUT1), // 1-bit MMCM clock output 1.CLKOUT1B(CLKOUT1B), // 1-bit Inverted MMCM clock output 1.CLKOUT2(CLKOUT2), // 1-bit MMCM clock output 2.CLKOUT2B(CLKOUT2B), // 1-bit Inverted MMCM clock output 2.CLKOUT3(CLKOUT3), // 1-bit MMCM clock output 3.CLKOUT3B(CLKOUT3B), // 1-bit Inverted MMCM clock output 3.CLKOUT4(CLKOUT4), // 1-bit MMCM clock output 4.CLKOUT5(CLKOUT5), // 1-bit MMCM clock output 5, not used if CLKOUT0 is not an integer.CLKOUT6(CLKOUT6), // 1-bit MMCM clock output 6, not used if CLKFBOUT_MULT is not an integer.LOCKED(LOCKED), // 1-bit MMC locked signal.CLKFBIN(CLKFBIN), // 1-bit Feedback clock pin to the MMCM.CLKIN1(CLKIN1), // 1-bit Reference clock pin 1 to the MMCM.PWRDWN(PWRDWN), // 1-bit Power down.RST(RST)// 1-bit MMCM global reset pin);// End of MMCM_BASE_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs228 www.xilinx.com UG623 (v 11.4) December 2, 2009
Chapter 4: About Design ElementsMUXF7Primitive: 2-to-1 Look-Up Table Multiplexer with General OutputIntroductionThis design element provides a multiplexer function for use in creating a function-of-7 look-up table or an 8-to-1multiplexer in combination with the associated look-up tables. Local outputs (LO) of MUXF6 are connectedto the I0 and I1 inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects I0.When High, S selects I1.The variants, “MUXF7_D” and “MUXF7_L”, provide additional types of outputs that can be used by differenttiming models for more accurate pre-layout timing estimation.Logic TableInputsOutputsS I0 I1 O0 I0 X I01 X I1 I1X 0 0 0X 1 1 1Port DescriptionsPort Direction Width FunctionO Output 1 Output of MUX to general routingI0 Input 1 Input (tie to MUXF6 LO out)I1 Input 1 Input (tie to MUXF6 LO out)S Input 1 Input select to MUXDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 229
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