Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsIBUFGDSPrimitive: Differential Signaling Dedicated Input Clock Buffer and Optional DelayIntroductionThis design element is a dedicated differential signaling input buffer for connection to the clock buffer (BUFG) orMMCM. In IBUFGDS, a design-level interface signal is represented as two distinct ports (I and IB), one deemedthe "master" and the other the "slave." The master and the slave are opposite phases of the same logical signal (forexample, MYNET_P and MYNET_N). Optionally, a programmable differential termination feature is available tohelp improve signal integrity and reduce external components. Also available is a programmable delay is toassist in the capturing of incoming data to the device.Logic TableInputsOutputsI IB O0 0 No Change0 1 01 0 11 1 No ChangePort DescriptionsPort Direction Width FunctionO Output 1 Clock Buffer outputIB Input 1 Diff_n Clock Buffer InputI Input 1 Diff_p Clock Buffer InputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoPut all I/O components on the top-level of the design to help facilitate hierarchical design methods. Connect the Iport directly to the top-level "master" input port of the design, the IB port to the top-level "slave" input port andthe O port to an MMCM, BUFG or logic in which this input is to source. Some synthesis tools infer the BUFGautomatically if necessary, when connecting an IBUFG to the clock resources of the FPGA. Specify the desiredgeneric/defparam values in order to configure the proper behavior of the buffer.Virtex-6 Libraries Guide for HDL Designs160 www.xilinx.com UG623 (v 11.4) December 2, 2009