Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsPort DescriptionsPort Direction Width FunctionDOA Output 1 Read port data outputs addressed by ADDRADOB Output 1 Read port data outputs addressed by ADDRBDOC Output 1 Read port data outputs addressed by ADDRCDOD Output 1 Read/Write port data outputs addressed byADDRDDIA Input 1 Write data inputs addressed by ADDRD (readoutput is addressed by ADDRA)DIB Input 1 Write data inputs addressed by ADDRD (readoutput is addressed by ADDRB)DIC Input 1 Write data inputs addressed by ADDRD (readoutput is addressed by ADDRC)DID Input 1 Write data inputs addressed by ADDRDADDRA Input 6 Read address bus AADDRB Input 6 Read address bus BADDRC Input 6 Read address bus CADDRD Input 6 4-bit data write port, 1-bit data read portaddress bus DWE Input 1 Write EnableWCLK Input 1 Write clock (reads are asynchronous)Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoThis element can be inferred by some synthesis tools by describing a RAM with a synchronous write andasynchronous read capability. Consult your synthesis tool documentation for details on RAM inferencecapabilities and coding examples. Xilinx suggests that you instantiate RAM64Ms if you have a need to implicitlyspecify the RAM function, or if you need to manually place or relationally place the component. If a synchronousread capability is desired, the RAM64M outputs can be connected to an FDRSE (FDCPE is asynchronous set/resetis necessary) in order to improve the output timing of the function. However, this is not necessary for theproper operation of the RAM. If you want to have the data clocked on the negative edge of a clock, an invertercan be described on the clock input to this component. This inverter will be absorbed into the block giving theability to write to the RAM on falling clock edges.If instantiated, the following connections should be made to this component. Tie the WCLK input to thedesired clock source, the DIA, DIB, DIC and DID inputs to the data source to be stored and the DOA, DOB,DOC and DOD outputs to an FDCE D input or other appropriate data destination or left unconnected if notused. The WE clock enable pin should be connected to the proper write enable source in the design. The 5-bitADDRD bus should be connected to the source for the read/write addressing and the 5-bit ADDRA, ADDRBand ADDRC buses should be connected to the appropriate read address connections. The optional INIT_A,INIT_B, INIT_C and INIT_D attributes consisting of a 64-bit hexadecimal values that specifies each port’s initialmemory contents can be specified. The INIT value correlates to the RAM addressing by the following equation:ADDRy[z] = INIT_y[z].Virtex-6 Libraries Guide for HDL Designs272 www.xilinx.com UG623 (v 11.4) December 2, 2009