Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsIntroductionThis design element is intended for use in conjunction with other resources located in the FPGA, such as theRocketIO transceivers, block RAMs, and various clocking resources. To implement an Endpoint, Root Port, orcustom PCI EXPRESS® design using PCIe_2_0, designers must use the CORE Generator software tool (part ofthe ISE® Design Suite) to create a LogiCORE IP core for PCI EXPRESS designs. The LogiCORE instantiatesthe PCIE_2_0 software primitive, connects the interfaces to the correct FPGA resources, sets all attributes, andpresents a simple, user-friendly interface.Design Entry MethodTo instantiate this component, use the PCI EXPRESS core or an associated core containing the component. Xilinxdoes not recommend direct instantiation of this component.For More Information• See the Virtex-6 FPGA RocketIO GTP Transceivers User Guide.• See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs256 www.xilinx.com UG623 (v 11.4) December 2, 2009