Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 2: About Unimacros// End of MULT_MACRO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs74 www.xilinx.com UG623 (v 11.4) December 2, 2009
Chapter 3Functional CategoriesThis section categorizes, by function, the circuit design elements described in detail later in this guide. Theelements ( primitives and macros) are listed in alphanumeric order under each functional category.Advanced Convenience Primitives RAM/ROMArithmetic Functions Gigabit I/O Registers/LatchesClock Components I/O Components Shift Register LUTConfig/BSCAN Components Logic Slice/CLB PrimitivesAdvancedDesign ElementPCIE_2_0SYSMONTEMAC_SINGLEDescriptionPrimitive: PCI Express version 2.0 Compliant.Primitive: System MonitorPrimitive: Tri-mode Ethernet Media Access Controller (MAC)Arithmetic FunctionsDesign ElementDSP48E1DescriptionPrimitive: 25x18 Two’s Complement Multiplier with Integrated 48-Bit, 3-InputAdder/Subtracter/Accumulator or 2-Input Logic UnitVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 75
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Virtex-6 Libraries Guide forHDL Des
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Table of ContentsXilinx Trademarks
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Available Attributes ..............
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Port Descriptions..................
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Chapter 1About this GuideThis HDL g
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Chapter 2About UnimacrosThis sectio
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Xilinx Virtex-6 Libraries Guide for HDL Designs

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