Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionINITIALPARITYHexadecimal256’h0000000000000000000000000000000000000000000000000000000000000000 to256’h000000000000000000000000000000000000000000001.15792089237316e+77All zerosAllows specification of the initialcontents of the 2 kb parity datamemory array.RAM_MODE String “TDP”,” SDP” “TDP” Selects simple dual port (SDP) or truedual port (TDP) mode.READ_WIDTH_A Integer 0, 1, 2, 4, 9, 18, 36, 72 0 Specifies the desired data width for aread on Port A, including parity bits.This value must be 0 if the Port A is notused. Otherwise, it should be set to thedesired port width. In SDP mode, thisis the read width including parity bits.READ_WIDTH_B Integer 0, 1, 2, 4, 9, 18 0 Specifies the desired data width for aread on Port B including parity bits.This value must be 0 if the Port B is notused. Otherwise, it should be set tothe desired port width. Not used forSDP mode.RSTREG_PRIORITY_A String “RSTREG”,“REGCE”RSTREG_PRIORITY_B String “RSTREG”,“REGCE”SIM_COLLISION_CHECKString“ALL”,”WARNING_ONLY”,”GENERATE_X_ONLY”,”NONE”“RSTREG”“RSTREG”“ALL”Selects register priority for RSTREGor REGCE. Applies to port A inTDP mode and up to 18 lower bits(including parity bits) in SDP mode.Selects register priority for RSTREGor REGCE. Applies to port B in TDPmode and upper bits (including paritybits) in SDP mode.Allows modification of the simulationbehavior if a memory collision occurs:• ALL - warning produced andaffected outputs/memory locationgo unknown (X).• WARNING_ONLY -warningproduced and affectedoutputs/memory retain lastvalue.• GENERATE_X_ONLY - nowarning however affectedoutputs/memory go unknown (X).• NONE - no warning and affectedoutputs/memory retain last value.Note ALL can allow problems inthe design go unnoticed duringsimulation. Care should be takenwhen changing the value of thisattribute.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 283