Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About UnimacrosMACC_MACROMacro: Multiplier/AccumulatorIntroductionThe MACC_MACRO simplifies the instantiation of the DSP48 block when used in simple signedmultiplier/accumulator mode. It features parameterizable input and output widths and latencies that ease theintegration of the DSP48 block into HDL.Port DescriptionName Direction Width FunctionOutput PortsP Output Variable width, equals the valueof the WIDTH_A attibute plus thevalue of the WIDTH_B attribute.Input PortsPrimary data output.A Input Variable, see WIDTH_A attribute. Multiplier data input.B Input Variable, see WIDTH_B attribute. Multiplier data input.CARRYIN Input 1 Carry input.CE Input 1 Clock enable.CLK Input 1 Clock.LOAD Inupt 1 Load.LOAD_DATA Input Variable width, equals the valueof the WIDTH_A attibute plus thevalue of the WIDTH_B attribute.In a DSP slice, when LOAD is asserted, loads Pwith A*B+LOAD_DATA.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 69