Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsBUFHCEPrimitive: Clock buffer for a single clocking region with clock enableIntroductionThis element is provided to allow instantiation access to HCLK clock buffer resources. In addition, it allows forpower reduction capabilities through disabling of the clock via clock enable (CE).Port DescriptionsPort Type Width FunctionCE Input 1 Enables propagation of signal from I to O. When low, sets outputto 0.I Input 1 The input to the BUFHO Output 1 The output of the BUFHDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT_OUT DECIMAL 0, 1 0 Initial output value. Also indicates Stop Low vs StopHigh behavior.VHDL Instantiation Template-- BUFHCE: Clock buffer for a single clocking region with clock enable-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.4BUFHCE_inst : BUFHCEgeneric map (INIT_OUT => 0 -- Initial output value, also indicates stop low vs stop high behavior)port map (O => O, -- 1-bit The output of the BUFHCE => CE, -- 1-bit Enables propagation of signal from I to O. When low, sets output to 0.I => I -- 1-bit The input to the BUFH);-- End of BUFHCE_inst instantiationVirtex-6 Libraries Guide for HDL Designs102 www.xilinx.com UG623 (v 11.4) December 2, 2009