Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About UnimacrosCOUNTER_LOAD_MACROMacro: Loadable CounterIntroductionThe COUNTER_LOAD_MACRO simplifies the instantiation of the DSP48 block when used as dynamic loadingup/down counter. It features parameterizable output width and count by values that ease the integrationof the DSP48 block into HDL.Port DescriptionName Direction Width FunctionOutput PortsQ Output Variable, see WIDTH_DATAattribute.Input PortsCounter output.DATA Input Variable, see WIDTH_DATA Data input (two-clock latency for variable data).attribute.CE Input 1 Clock Enable.CLK Input 1 Clock.LOAD Input Variable, see WIDTH_DATAattribute.LOAD_DATA Input Variable, see WIDTH_DATAattribute.When asserted, loads the counter fromLOAD_DATA (two-clock latency).In a DSP slice, asserting the LOAD pin will forcethis data into the P register with a latency of 2clocks.DIRECTION Input 1 High for Up and Low for Down (two-clocklatency)RST Input 1 Synchronous ResetDesign Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive.Virtex-6 Libraries Guide for HDL Designs60 www.xilinx.com UG623 (v 11.4) December 2, 2009