Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 1About this GuideThis HDL guide is part of the ISE documentation collection. A separate version of this guide is available if youprefer to work with schematics.This guide contains the following:• Introduction.• A list of design elements supported in this architecture, organized by functional categories.• Individual descriptions of each available primitive.Design Entry MethodsFor each design element in this guide, Xilinx evaluates the four options and recommends what we believe is thebest solution for you. The four options are:• Instantiation - This component can be instantiated directly into the design. This method is useful if you wantto control the exact placement of the individual blocks.• Inference - This component can be inferred by most supported synthesis tools. You should use this method ifyou want to have complete flexibility and portability of the code to multiple architectures. Inference also givesthe tools the ability to optimize for performance, area, or power, as specified by the user to the synthesis tool.• Coregen & Wizards - This component can be used through Coregen or Wizards. You should use this methodif you want to build large blocks of any FPGA primitive that cannot be inferred. When using this flow, youwill have to re-generate your cores for each architecture that you are targeting.• Macro Support - This component has a UniMacro that can be used. These components are in the UniMacrolibrary in the Xilinx tool, and are used to instantiate primitives that are complex to instantiate by just usingthe primitives. The synthesis tools will automatically expand the unimacros to their underlying primitives.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 15