Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsPort Type Width FunctionCLKFBSTOPPED Output 1 Status pin indicating that the feedback clock has stopped.CLKINSEL Input 1 Signal controls the state of the clock input MUX, High = CLKIN1,Low = CLKIN2. Dynamically switches the MMCM reference clock.CLKINSTOPPED Output 1 Status pin indicating that the input clock has stopped.CLKIN1 Input 1 General clock input.CLKIN2 Input 1 Secondary clock input for the MMCM reference clock.CLKOUT[0:6] Output 7, 1–bit User configurable clock outputs (0 through 6) that can be dividedversions of the VCO phase outputs (user controllable) from 1(bypassed) to 128. The output clocks are phase aligned to eachother (unless phase shifted) and aligned to the input clock with aproper feedback configuration.CLKOUT[0:3]B Output 4, 1–bit Inverted CLKOUT[0:3].DADDR[6:0] Input 7 The dynamic reconfiguration address (DADDR) inputbus provides a reconfiguration address for the dynamicreconfiguration. When not used, all bits must be assigned zeros.DCLK Input 1 The DCLK signal is the reference clock for the dynamicreconfiguration port.DEN Input 1 The dynamic reconfiguration enable (DEN) provides the enablecontrol signal to access the dynamic reconfiguration feature.When the dynamic reconfiguration feature is not used, DEN mustbe tied Low.DI[15:0] Input 16 The dynamic reconfiguration data input (DI) bus providesreconfiguration data. When not used, all bits must be set to zero.DO[15:0] Output 16 The dynamic reconfiguration output bus provides MMCM dataoutput when using dynamic reconfiguration.DRDY Output 1 The dynamic reconfiguration ready (DRDY) output providesthe response to the DEN signal for the MMCMs dynamicreconfiguration feature.DWE Input 1 The dynamic reconfiguration write enable (DWE) input pinprovides the write enable control signal to write the DI data intothe DADDR address. When not used, it must be tied Low.LOCKED Output 1 An output from the MMCM that indicates when the MMCMhas achieved phase alignment within a predefined window andfrequency matching within a predefined PPM range. The MMCMautomatically locks after power on. No extra reset is required.LOCKED will be deasserted if the input clock stops or the phasealignment is violated (e.g., input clock phase shift). The MMCMautomatically reacquires lock after LOCKED is deasserted.PSCLK Input 1 Phase shift clock.PSDONE Output 1 Phase shift done.PSEN Input 1 Phase shift enable.PSINCDEC Input 1 Phase shift Increment/Decrement control.PWRDWN Input 1 Powers down instantiated but unused MMCMs.RST Input 1 Asynchronous reset signal. The RST signal is an asynchronousreset for the MMCM. The MMCM will synchronously re-enableitself when this signal is released (i.e., MMCM re-enabled). Areset is not required when the input clock conditions change (e.g.,frequency).Virtex-6 Libraries Guide for HDL Designs218 www.xilinx.com UG623 (v 11.4) December 2, 2009