Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// BUFGCE_1: Global Clock Buffer with Clock Enable (active low)// Virtex-4/5/6, Spartan-3/3E/3A/6// Xilinx HDL Libraries Guide, version 11.2BUFGCE_1 BUFGCE_1_inst (.O(O), // Clock buffer output.CE(CE), // Clock enable input.I(I) // Clock buffer input);// End of BUFGCE_1_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 91