Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// RAM64M: 64-deep by 4-wide Multi Port LUT RAM// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2RAM64M #(.INIT_A(64’h0000000000000000), // Initial contents of A Port.INIT_B(64’h0000000000000000), // Initial contents of B Port.INIT_C(64’h0000000000000000), // Initial contents of C Port.INIT_D(64’h0000000000000000) // Initial contents of D Port) RAM64M_inst (.DOA(DOA), // Read port A 1-bit output.DOB(DOB), // Read port B 1-bit output.DOC(DOC), // Read port C 1-bit output.DOD(DOD), // Read/Write port D 1-bit output.DIA(DIA), // RAM 1-bit data write input addressed by ADDRD,// read addressed by ADDRA.DIB(DIB), // RAM 1-bit data write input addressed by ADDRD,// read addressed by ADDRB.DIC(DIC), // RAM 1-bit data write input addressed by ADDRD,.DID(DID),// read addressed by ADDRC// RAM 1-bit data write input addressed by ADDRD,// read addressed by ADDRD.ADDRA(ADDRA), // Read port A 6-bit address input.ADDRB(ADDRB), // Read port B 6-bit address input.ADDRC(ADDRC), // Read port C 6-bit address input.ADDRD(ADDRD), // Read/Write port D 6-bit address input.WE(WE),.WCLK(WCLK));// Write enable input// Write clock input// End of RAM64M_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs274 www.xilinx.com UG623 (v 11.4) December 2, 2009