Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsPort Type Width FunctionEMPTY Output 1 Active High logic to indicate that the FIFO is currentlyempty.FULL Output 1 Active High logic indicates that the FIFO is full.RDEN Input 1 Active High FIFO read enable.REGCE Input 1 Output register clock enable for pipelined synchronousFIFO.RST Input 1 Active High (FIFO logic) asynchronous reset (for dual-clockFIFO), synchronous reset (synchronous FIFO) for 3 CLKcycles.RSTREG Input 1 Output register synchronous set/reset.WRCLK,RDCLKWRCOUNT,RDCOUNTInput 1 FIFO read and write clocks (positive edge triggered).Output 12 FIFO write/read pointer.WREN Input 1 Active High FIFO write enable.WRERR,RDERROutput 1 • WRERR indicates that a write occurred while the FIFOwas full.• RDERR indicates that a read occurred while the FIFOwas empty.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedAvailable AttributesAttribute Type Allowed Values Default DescriptionALMOST_EMPTY_OFFSETALMOST_FULL_OFFSETHexadecimalHexadecimal13’h0000 to13’h819113’h0000 to13’h819113’h0080 Specifies the amount of datacontents in the RAM to trigger theALMOST_EMPTY flag.13’h0080 Specifies the amount of datacontents in the RAM to trigger theALMOST_FULL flag.DATA_WIDTH Integer 4, 9, 18, 36 4 Specifies the desired data width forthe FIFO.DO_REG Integer 1, 0 1 Data pipeline register for EN_SYN.EN_SYN Boolean FALSE, TRUE FALSE Specifies whether the FIFO is operatingin either dual-clock (two independentclocks) or synchronous (singleclock) mode. Dual-clock must useDO_REG=1.FIFO_MODE String “FIFO18”,“FIFO18_36”“FIFO18”Selects FIFO18 or FIFO18_36 mode.Virtex-6 Libraries Guide for HDL Designs138 www.xilinx.com UG623 (v 11.4) December 2, 2009