Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About UnimacrosAttribute Type Allowed Values Default DescriptionDO_REG Integer 0, 1 0 A value of 1 enables to the outputregisters to the RAM enabling quickerclock-to-out from the RAM at theexpense of an added clock cycle ofread latency. A value of 0 allows aread in one clock cycle but will haveslower clock to out timing.INIT Hexadecimal Any 72-Bit Value All zeros Specifies the initial value on theoutput after configuration.READ_WIDTH,WRITE_WIDTHInteger 1-72 36 Specifies size of DI/DO bus.READ_WIDTH and WRITE_WIDTHmust be equal.INIT_FILE String 0 bit string “NONE” Name of the file containing initialvalues.SIM_COLLISION_CHECKString“ALL,”"WARNING_ONLY","GENERATE_X_ONLY","NONE”“ALL”Allows modification of the simulationbehavior if a memory collision occurs.The output is affected as follows:• "ALL" - Warning producedand affected outputs/memorylocation go unknown (X).• "WARNING_ONLY" - Warningproduced and affectedoutputs/memory retain lastvalue.• "GENERATE_X_ONLY" - Nowarning. However, affectedoutputs/memory go unknown(X).• "NONE" - No warning andaffected outputs/memory retainlast value.Note Setting this to a value otherthan "ALL" can allow problems inthe design go unnoticed duringsimulation. Care should be takenwhen changing the value of thisattribute. Please see the Synthesisand Simulation Design Guide for moreinformation.SIM_MODE String "SAFE" or "FAST" . "SAFE" This is a simulation only attribute. Itwill direct the simulation model torun in performance-oriented modewhen set to "FAST." Please see theSynthesis and Simulation Design Guidefor more information.SRVAL Hexadecimal Any 72-Bit Value All zeroes Specifies the output value of on theDO port upon the assertion of thesynchronous reset (RST) signal.INIT_00 toINIT_7FINITP_00 toINITP_0FHexadecimal Any 256-Bit Value All zeroes Allows specification of the initialcontents of the 16kb or 32kb datamemory array.Hexadecimal Any 256-Bit Value All zeroes Allows specification of the initialcontents of the 2kb or 4kb parity datamemory array.Virtex-6 Libraries Guide for HDL Designs20 www.xilinx.com UG623 (v 11.4) December 2, 2009