Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// DCIRESET: Digital Controlled Impedance (DCI) Reset Component// Virtex-4// Xilinx HDL Libraries Guide, version 11.2DCIRESET DCIRESET_inst (.LOCKED(LOCKED), // 1-bit DCI LOCKED Output.RST(RST)// 1-bit DCI Reset Input);// End of DCIRESET_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs118 www.xilinx.com UG623 (v 11.4) December 2, 2009